466 lines
22 KiB
ArmAsm
466 lines
22 KiB
ArmAsm
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/*
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* Copyright (c) 2013-2018 Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* -----------------------------------------------------------------------------
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*
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* Project: CMSIS-RTOS RTX
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* Title: Cortex-A Exception handlers
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*
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* -----------------------------------------------------------------------------
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*/
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.file "irq_ca.S"
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.syntax unified
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.equ MODE_FIQ, 0x11
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.equ MODE_IRQ, 0x12
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.equ MODE_SVC, 0x13
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.equ MODE_ABT, 0x17
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.equ MODE_UND, 0x1B
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.equ CPSR_BIT_T, 0x20
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.equ K_STATE_RUNNING, 2 // osKernelState_t::osKernelRunning
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.equ I_K_STATE_OFS, 8 // osRtxInfo.kernel.state offset
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.equ I_TICK_IRQN_OFS, 16 // osRtxInfo.tick_irqn offset
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.equ I_T_RUN_OFS, 20 // osRtxInfo.thread.run offset
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.equ TCB_SP_FRAME, 34 // osRtxThread_t.stack_frame offset
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.equ TCB_SP_OFS, 56 // osRtxThread_t.sp offset
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.section ".rodata"
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.global irqRtxLib // Non weak library reference
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irqRtxLib:
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.byte 0
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.section ".data"
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.global IRQ_PendSV
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IRQ_NestLevel:
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.word 0 // IRQ nesting level counter
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IRQ_PendSV:
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.byte 0 // Pending SVC flag
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.arm
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.section ".text"
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.align 4
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.type Undef_Handler, %function
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.global Undef_Handler
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.fnstart
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.cantunwind
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Undef_Handler:
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SRSFD SP!, #MODE_UND
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PUSH {R0-R4, R12} // Save APCS corruptible registers to UND mode stack
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MRS R0, SPSR
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TST R0, #CPSR_BIT_T // Check mode
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MOVEQ R1, #4 // R1 = 4 ARM mode
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MOVNE R1, #2 // R1 = 2 Thumb mode
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SUB R0, LR, R1
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LDREQ R0, [R0] // ARM mode - R0 points to offending instruction
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BEQ Undef_Cont
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// Thumb instruction
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// Determine if it is a 32-bit Thumb instruction
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LDRH R0, [R0]
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MOV R2, #0x1C
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CMP R2, R0, LSR #11
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BHS Undef_Cont // 16-bit Thumb instruction
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// 32-bit Thumb instruction. Unaligned - reconstruct the offending instruction
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LDRH R2, [LR]
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ORR R0, R2, R0, LSL #16
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Undef_Cont:
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MOV R2, LR // Set LR to third argument
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AND R12, SP, #4 // Ensure stack is 8-byte aligned
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SUB SP, SP, R12 // Adjust stack
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PUSH {R12, LR} // Store stack adjustment and dummy LR
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// R0 =Offending instruction, R1 =2(Thumb) or =4(ARM)
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BL CUndefHandler
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POP {R12, LR} // Get stack adjustment & discard dummy LR
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ADD SP, SP, R12 // Unadjust stack
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LDR LR, [SP, #24] // Restore stacked LR and possibly adjust for retry
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SUB LR, LR, R0
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LDR R0, [SP, #28] // Restore stacked SPSR
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MSR SPSR_cxsf, R0
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CLREX // Clear exclusive monitor
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POP {R0-R4, R12} // Restore stacked APCS registers
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ADD SP, SP, #8 // Adjust SP for already-restored banked registers
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MOVS PC, LR
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.fnend
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.size Undef_Handler, .-Undef_Handler
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.type PAbt_Handler, %function
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.global PAbt_Handler
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.fnstart
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.cantunwind
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PAbt_Handler:
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SUB LR, LR, #4 // Pre-adjust LR
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SRSFD SP!, #MODE_ABT // Save LR and SPRS to ABT mode stack
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PUSH {R0-R4, R12} // Save APCS corruptible registers to ABT mode stack
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MRC p15, 0, R0, c5, c0, 1 // IFSR
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MRC p15, 0, R1, c6, c0, 2 // IFAR
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MOV R2, LR // Set LR to third argument
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AND R12, SP, #4 // Ensure stack is 8-byte aligned
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SUB SP, SP, R12 // Adjust stack
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PUSH {R12, LR} // Store stack adjustment and dummy LR
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BL CPAbtHandler
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POP {R12, LR} // Get stack adjustment & discard dummy LR
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ADD SP, SP, R12 // Unadjust stack
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CLREX // Clear exclusive monitor
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POP {R0-R4, R12} // Restore stack APCS registers
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RFEFD SP! // Return from exception
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.fnend
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.size PAbt_Handler, .-PAbt_Handler
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.type DAbt_Handler, %function
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.global DAbt_Handler
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.fnstart
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.cantunwind
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DAbt_Handler:
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SUB LR, LR, #8 // Pre-adjust LR
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SRSFD SP!, #MODE_ABT // Save LR and SPRS to ABT mode stack
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PUSH {R0-R4, R12} // Save APCS corruptible registers to ABT mode stack
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MRC p15, 0, R0, c5, c0, 0 // DFSR
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MRC p15, 0, R1, c6, c0, 0 // DFAR
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MOV R2, LR // Set LR to third argument
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AND R12, SP, #4 // Ensure stack is 8-byte aligned
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SUB SP, SP, R12 // Adjust stack
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PUSH {R12, LR} // Store stack adjustment and dummy LR
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BL CDAbtHandler
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POP {R12, LR} // Get stack adjustment & discard dummy LR
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ADD SP, SP, R12 // Unadjust stack
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CLREX // Clear exclusive monitor
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POP {R0-R4, R12} // Restore stacked APCS registers
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RFEFD SP! // Return from exception
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.fnend
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.size DAbt_Handler, .-DAbt_Handler
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.type IRQ_Handler, %function
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.global IRQ_Handler
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.fnstart
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.cantunwind
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IRQ_Handler:
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SUB LR, LR, #4 // Pre-adjust LR
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SRSFD SP!, #MODE_SVC // Save LR_irq and SPSR_irq on to the SVC stack
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CPS #MODE_SVC // Change to SVC mode
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PUSH {R0-R3, R12, LR} // Save APCS corruptible registers
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LDR R0, =IRQ_NestLevel
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LDR R1, [R0]
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ADD R1, R1, #1 // Increment IRQ nesting level
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STR R1, [R0]
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MOV R3, SP // Move SP into R3
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AND R3, R3, #4 // Get stack adjustment to ensure 8-byte alignment
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SUB SP, SP, R3 // Adjust stack
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PUSH {R3, R4} // Store stack adjustment(R3) and user data(R4)
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BLX IRQ_GetActiveIRQ // Retrieve interrupt ID into R0
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MOV R4, R0 // Move interrupt ID to R4
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BLX IRQ_GetHandler // Retrieve interrupt handler address for current ID
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CMP R0, #0 // Check if handler address is 0
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BEQ IRQ_End // If 0, end interrupt and return
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CPSIE i // Re-enable interrupts
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BLX R0 // Call IRQ handler
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CPSID i // Disable interrupts
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IRQ_End:
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MOV R0, R4 // Move interrupt ID to R0
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BLX IRQ_EndOfInterrupt // Signal end of interrupt
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POP {R3, R4} // Restore stack adjustment(R3) and user data(R4)
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ADD SP, SP, R3 // Unadjust stack
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BL osRtxContextSwitch // Continue in context switcher
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LDR R0, =IRQ_NestLevel
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LDR R1, [R0]
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SUBS R1, R1, #1 // Decrement IRQ nesting level
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STR R1, [R0]
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CLREX // Clear exclusive monitor for interrupted code
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POP {R0-R3, R12, LR} // Restore stacked APCS registers
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RFEFD SP! // Return from IRQ handler
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.fnend
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.size IRQ_Handler, .-IRQ_Handler
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.type SVC_Handler, %function
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.global SVC_Handler
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.fnstart
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.cantunwind
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SVC_Handler:
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SRSFD SP!, #MODE_SVC // Store SPSR_svc and LR_svc onto SVC stack
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PUSH {R12, LR}
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MRS R12, SPSR // Load SPSR
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TST R12, #CPSR_BIT_T // Thumb bit set?
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LDRHNE R12, [LR,#-2] // Thumb: load halfword
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BICNE R12, R12, #0xFF00 // extract SVC number
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LDREQ R12, [LR,#-4] // ARM: load word
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BICEQ R12, R12, #0xFF000000 // extract SVC number
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CMP R12, #0 // Compare SVC number
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BNE SVC_User // Branch if User SVC
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PUSH {R0-R3}
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LDR R0, =IRQ_NestLevel
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LDR R1, [R0]
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ADD R1, R1, #1 // Increment IRQ nesting level
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STR R1, [R0]
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LDR R0, =osRtxInfo
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LDR R1, [R0, #I_K_STATE_OFS] // Load RTX5 kernel state
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CMP R1, #K_STATE_RUNNING // Check osKernelRunning
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BLT SVC_FuncCall // Continue if kernel is not running
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LDR R0, [R0, #I_TICK_IRQN_OFS] // Load OS Tick irqn
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BLX IRQ_Disable // Disable OS Tick interrupt
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SVC_FuncCall:
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POP {R0-R3}
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LDR R12, [SP] // Reload R12 from stack
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CPSIE i // Re-enable interrupts
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BLX R12 // Branch to SVC function
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CPSID i // Disable interrupts
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SUB SP, SP, #4
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STM SP, {SP}^ // Store SP_usr onto stack
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POP {R12} // Pop SP_usr into R12
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SUB R12, R12, #16 // Adjust pointer to SP_usr
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LDMDB R12, {R2,R3} // Load return values from SVC function
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PUSH {R0-R3} // Push return values to stack
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LDR R0, =osRtxInfo
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LDR R1, [R0, #I_K_STATE_OFS] // Load RTX5 kernel state
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CMP R1, #K_STATE_RUNNING // Check osKernelRunning
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BLT SVC_ContextCheck // Continue if kernel is not running
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LDR R0, [R0, #I_TICK_IRQN_OFS] // Load OS Tick irqn
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BLX IRQ_Enable // Enable OS Tick interrupt
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SVC_ContextCheck:
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BL osRtxContextSwitch // Continue in context switcher
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LDR R0, =IRQ_NestLevel
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LDR R1, [R0]
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SUB R1, R1, #1 // Decrement IRQ nesting level
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STR R1, [R0]
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CLREX // Clear exclusive monitor
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POP {R0-R3, R12, LR} // Restore stacked APCS registers
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RFEFD SP! // Return from exception
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SVC_User:
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PUSH {R4, R5}
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LDR R5,=osRtxUserSVC // Load address of SVC table
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LDR R4,[R5] // Load SVC maximum number
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CMP R12,R4 // Check SVC number range
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BHI SVC_Done // Branch if out of range
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LDR R12,[R5,R12,LSL #2] // Load SVC Function Address
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BLX R12 // Call SVC Function
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SVC_Done:
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CLREX // Clear exclusive monitor
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POP {R4, R5, R12, LR}
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RFEFD SP! // Return from exception
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.fnend
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.size SVC_Handler, .-SVC_Handler
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.type osRtxContextSwitch, %function
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.global osRtxContextSwitch
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.fnstart
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.cantunwind
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osRtxContextSwitch:
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PUSH {LR}
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// Check interrupt nesting level
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LDR R0, =IRQ_NestLevel
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LDR R1, [R0] // Load IRQ nest level
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CMP R1, #1
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BNE osRtxContextExit // Nesting interrupts, exit context switcher
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LDR R12, =osRtxInfo+I_T_RUN_OFS // Load address of osRtxInfo.run
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LDM R12, {R0, R1} // Load osRtxInfo.thread.run: curr & next
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LDR R2, =IRQ_PendSV // Load address of IRQ_PendSV flag
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LDRB R3, [R2] // Load PendSV flag
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CMP R0, R1 // Check if context switch is required
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BNE osRtxContextCheck // Not equal, check if context save required
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CMP R3, #1 // Compare IRQ_PendSV value
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BNE osRtxContextExit // No post processing (and no context switch requested)
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osRtxContextCheck:
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STR R1, [R12] // Store run.next as run.curr
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// R0 = curr, R1 = next, R2 = &IRQ_PendSV, R3 = IRQ_PendSV, R12 = &osRtxInfo.thread.run
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PUSH {R1-R3, R12}
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CMP R0, #0 // Is osRtxInfo.thread.run.curr == 0
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BEQ osRtxPostProcess // Current deleted, skip context save
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osRtxContextSave:
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MOV LR, R0 // Move &osRtxInfo.thread.run.curr to LR
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MOV R0, SP // Move SP_svc into R0
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ADD R0, R0, #20 // Adjust SP_svc to R0 of the basic frame
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SUB SP, SP, #4
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STM SP, {SP}^ // Save SP_usr to current stack
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POP {R1} // Pop SP_usr into R1
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SUB R1, R1, #64 // Adjust SP_usr to R4 of the basic frame
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STMIA R1!, {R4-R11} // Save R4-R11 to user stack
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LDMIA R0!, {R4-R8} // Load stacked R0-R3,R12 into R4-R8
|
||
|
|
STMIA R1!, {R4-R8} // Store them to user stack
|
||
|
|
STM R1, {LR}^ // Store LR_usr directly
|
||
|
|
ADD R1, R1, #4 // Adjust user sp to PC
|
||
|
|
LDMIB R0!, {R5-R6} // Load current PC, CPSR
|
||
|
|
STMIA R1!, {R5-R6} // Restore user PC and CPSR
|
||
|
|
|
||
|
|
SUB R1, R1, #64 // Adjust SP_usr to stacked R4
|
||
|
|
|
||
|
|
// Check if VFP state need to be saved
|
||
|
|
MRC p15, 0, R2, c1, c0, 2 // VFP/NEON access enabled? (CPACR)
|
||
|
|
AND R2, R2, #0x00F00000
|
||
|
|
CMP R2, #0x00F00000
|
||
|
|
BNE osRtxContextSave1 // Continue, no VFP
|
||
|
|
|
||
|
|
VMRS R2, FPSCR
|
||
|
|
STMDB R1!, {R2,R12} // Push FPSCR, maintain 8-byte alignment
|
||
|
|
|
||
|
|
VSTMDB R1!, {D0-D15} // Save D0-D15
|
||
|
|
#if __ARM_NEON == 1
|
||
|
|
VSTMDB R1!, {D16-D31} // Save D16-D31
|
||
|
|
#endif
|
||
|
|
|
||
|
|
LDRB R2, [LR, #TCB_SP_FRAME] // Load osRtxInfo.thread.run.curr frame info
|
||
|
|
#if __ARM_NEON == 1
|
||
|
|
ORR R2, R2, #4 // NEON state
|
||
|
|
#else
|
||
|
|
ORR R2, R2, #2 // VFP state
|
||
|
|
#endif
|
||
|
|
STRB R2, [LR, #TCB_SP_FRAME] // Store VFP/NEON state
|
||
|
|
|
||
|
|
osRtxContextSave1:
|
||
|
|
STR R1, [LR, #TCB_SP_OFS] // Store user sp to osRtxInfo.thread.run.curr
|
||
|
|
|
||
|
|
osRtxPostProcess:
|
||
|
|
// RTX IRQ post processing check
|
||
|
|
POP {R8-R11} // Pop R8 = run.next, R9 = &IRQ_PendSV, R10 = IRQ_PendSV, R11 = &osRtxInfo.thread.run
|
||
|
|
CMP R10, #1 // Compare PendSV value
|
||
|
|
BNE osRtxContextRestore // Skip post processing if not pending
|
||
|
|
|
||
|
|
MOV R4, SP // Move SP_svc into R4
|
||
|
|
AND R4, R4, #4 // Get stack adjustment to ensure 8-byte alignment
|
||
|
|
SUB SP, SP, R4 // Adjust stack
|
||
|
|
|
||
|
|
// Disable OS Tick
|
||
|
|
LDR R5, =osRtxInfo // Load address of osRtxInfo
|
||
|
|
LDR R5, [R5, #I_TICK_IRQN_OFS] // Load OS Tick irqn
|
||
|
|
MOV R0, R5 // Set it as function parameter
|
||
|
|
BLX IRQ_Disable // Disable OS Tick interrupt
|
||
|
|
MOV R6, #0 // Set PendSV clear value
|
||
|
|
B osRtxPendCheck
|
||
|
|
osRtxPendExec:
|
||
|
|
STRB R6, [R9] // Clear PendSV flag
|
||
|
|
CPSIE i // Re-enable interrupts
|
||
|
|
BLX osRtxPendSV_Handler // Post process pending objects
|
||
|
|
CPSID i // Disable interrupts
|
||
|
|
osRtxPendCheck:
|
||
|
|
LDR R8, [R11, #4] // Load osRtxInfo.thread.run.next
|
||
|
|
STR R8, [R11] // Store run.next as run.curr
|
||
|
|
LDRB R0, [R9] // Load PendSV flag
|
||
|
|
CMP R0, #1 // Compare PendSV value
|
||
|
|
BEQ osRtxPendExec // Branch to PendExec if PendSV is set
|
||
|
|
|
||
|
|
// Re-enable OS Tick
|
||
|
|
MOV R0, R5 // Restore irqn as function parameter
|
||
|
|
BLX IRQ_Enable // Enable OS Tick interrupt
|
||
|
|
|
||
|
|
ADD SP, SP, R4 // Restore stack adjustment
|
||
|
|
|
||
|
|
osRtxContextRestore:
|
||
|
|
LDR LR, [R8, #TCB_SP_OFS] // Load next osRtxThread_t.sp
|
||
|
|
LDRB R2, [R8, #TCB_SP_FRAME] // Load next osRtxThread_t.stack_frame
|
||
|
|
|
||
|
|
ANDS R2, R2, #0x6 // Check stack frame for VFP context
|
||
|
|
MRC p15, 0, R2, c1, c0, 2 // Read CPACR
|
||
|
|
ANDEQ R2, R2, #0xFF0FFFFF // VFP/NEON state not stacked, disable VFP/NEON
|
||
|
|
ORRNE R2, R2, #0x00F00000 // VFP/NEON state is stacked, enable VFP/NEON
|
||
|
|
MCR p15, 0, R2, c1, c0, 2 // Write CPACR
|
||
|
|
BEQ osRtxContextRestore1 // No VFP
|
||
|
|
ISB // Sync if VFP was enabled
|
||
|
|
#if __ARM_NEON == 1
|
||
|
|
VLDMIA LR!, {D16-D31} // Restore D16-D31
|
||
|
|
#endif
|
||
|
|
VLDMIA LR!, {D0-D15} // Restore D0-D15
|
||
|
|
LDR R2, [LR]
|
||
|
|
VMSR FPSCR, R2 // Restore FPSCR
|
||
|
|
ADD LR, LR, #8 // Adjust sp pointer to R4
|
||
|
|
|
||
|
|
osRtxContextRestore1:
|
||
|
|
LDMIA LR!, {R4-R11} // Restore R4-R11
|
||
|
|
ADD R12, LR, #32 // Adjust sp and save it into R12
|
||
|
|
PUSH {R12} // Push sp onto stack
|
||
|
|
LDM SP, {SP}^ // Restore SP_usr directly
|
||
|
|
ADD SP, SP, #4 // Adjust SP_svc
|
||
|
|
LDMIA LR!, {R0-R3, R12} // Load user registers R0-R3,R12
|
||
|
|
STMIB SP!, {R0-R3, R12} // Store them to SP_svc
|
||
|
|
LDM LR, {LR}^ // Restore LR_usr directly
|
||
|
|
LDMIB LR!, {R0-R1} // Load user registers PC,CPSR
|
||
|
|
ADD SP, SP, #4
|
||
|
|
STMIB SP!, {R0-R1} // Store them to SP_svc
|
||
|
|
SUB SP, SP, #32 // Adjust SP_svc to stacked LR
|
||
|
|
|
||
|
|
osRtxContextExit:
|
||
|
|
POP {PC} // Return
|
||
|
|
|
||
|
|
.fnend
|
||
|
|
.size osRtxContextSwitch, .-osRtxContextSwitch
|
||
|
|
|
||
|
|
.end
|