334 lines
14 KiB
ArmAsm
334 lines
14 KiB
ArmAsm
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;/*
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; * Copyright (c) 2016-2018 Arm Limited. All rights reserved.
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; *
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; * SPDX-License-Identifier: Apache-2.0
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; *
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; * Licensed under the Apache License, Version 2.0 (the License); you may
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; * not use this file except in compliance with the License.
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; * You may obtain a copy of the License at
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; *
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; * www.apache.org/licenses/LICENSE-2.0
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; *
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; * Unless required by applicable law or agreed to in writing, software
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; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
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; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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; * See the License for the specific language governing permissions and
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; * limitations under the License.
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; *
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; * -----------------------------------------------------------------------------
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; *
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; * Project: CMSIS-RTOS RTX
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; * Title: ARMv8M Baseline Exception handlers
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; *
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; * -----------------------------------------------------------------------------
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; */
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IF :LNOT::DEF:DOMAIN_NS
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DOMAIN_NS EQU 0
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ENDIF
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I_T_RUN_OFS EQU 20 ; osRtxInfo.thread.run offset
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TCB_SM_OFS EQU 48 ; TCB.stack_mem offset
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TCB_SP_OFS EQU 56 ; TCB.SP offset
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TCB_SF_OFS EQU 34 ; TCB.stack_frame offset
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TCB_TZM_OFS EQU 64 ; TCB.tz_memory offset
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PRESERVE8
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THUMB
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AREA |.constdata|, DATA, READONLY
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EXPORT irqRtxLib
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irqRtxLib DCB 0 ; Non weak library reference
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AREA |.text|, CODE, READONLY
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SVC_Handler PROC
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EXPORT SVC_Handler
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IMPORT osRtxUserSVC
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IMPORT osRtxInfo
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IF :DEF:MPU_LOAD
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IMPORT osRtxMpuLoad
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ENDIF
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IF DOMAIN_NS = 1
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IMPORT TZ_LoadContext_S
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IMPORT TZ_StoreContext_S
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ENDIF
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MOV R0,LR
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LSRS R0,R0,#3 ; Determine return stack from EXC_RETURN bit 2
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BCC SVC_MSP ; Branch if return stack is MSP
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MRS R0,PSP ; Get PSP
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SVC_Number
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LDR R1,[R0,#24] ; Load saved PC from stack
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SUBS R1,R1,#2 ; Point to SVC instruction
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LDRB R1,[R1] ; Load SVC number
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CMP R1,#0
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BNE SVC_User ; Branch if not SVC 0
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PUSH {R0,LR} ; Save SP and EXC_RETURN
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LDM R0,{R0-R3} ; Load function parameters from stack
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BLX R7 ; Call service function
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POP {R2,R3} ; Restore SP and EXC_RETURN
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STMIA R2!,{R0-R1} ; Store function return values
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MOV LR,R3 ; Set EXC_RETURN
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SVC_Context
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LDR R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.run
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LDMIA R3!,{R1,R2} ; Load osRtxInfo.thread.run: curr & next
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CMP R1,R2 ; Check if thread switch is required
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BEQ SVC_Exit ; Branch when threads are the same
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CBZ R1,SVC_ContextSwitch ; Branch if running thread is deleted
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SVC_ContextSave
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IF DOMAIN_NS = 1
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LDR R0,[R1,#TCB_TZM_OFS] ; Load TrustZone memory identifier
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CBZ R0,SVC_ContextSave1 ; Branch if there is no secure context
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PUSH {R1,R2,R3,R7} ; Save registers
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MOV R7,LR ; Get EXC_RETURN
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BL TZ_StoreContext_S ; Store secure context
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MOV LR,R7 ; Set EXC_RETURN
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POP {R1,R2,R3,R7} ; Restore registers
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ENDIF
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SVC_ContextSave1
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MRS R0,PSP ; Get PSP
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SUBS R0,R0,#32 ; Calculate SP
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STR R0,[R1,#TCB_SP_OFS] ; Store SP
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STMIA R0!,{R4-R7} ; Save R4..R7
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MOV R4,R8
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MOV R5,R9
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MOV R6,R10
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MOV R7,R11
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STMIA R0!,{R4-R7} ; Save R8..R11
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SVC_ContextSave2
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MOV R0,LR ; Get EXC_RETURN
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ADDS R1,R1,#TCB_SF_OFS ; Adjust address
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STRB R0,[R1] ; Store stack frame information
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SVC_ContextSwitch
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SUBS R3,R3,#8 ; Adjust address
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STR R2,[R3] ; osRtxInfo.thread.run: curr = next
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IF :DEF:MPU_LOAD
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PUSH {R2,R3} ; Save registers
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MOV R0,R2 ; osRtxMpuLoad parameter
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BL osRtxMpuLoad ; Load MPU for next thread
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POP {R2,R3} ; Restore registers
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ENDIF
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SVC_ContextRestore
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IF DOMAIN_NS = 1
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LDR R0,[R2,#TCB_TZM_OFS] ; Load TrustZone memory identifier
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CBZ R0,SVC_ContextRestore1 ; Branch if there is no secure context
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PUSH {R2,R3} ; Save registers
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BL TZ_LoadContext_S ; Load secure context
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POP {R2,R3} ; Restore registers
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ENDIF
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SVC_ContextRestore1
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MOV R1,R2
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ADDS R1,R1,#TCB_SF_OFS ; Adjust address
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LDRB R0,[R1] ; Load stack frame information
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MOVS R1,#0xFF
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MVNS R1,R1 ; R1=0xFFFFFF00
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ORRS R0,R1
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MOV LR,R0 ; Set EXC_RETURN
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IF DOMAIN_NS = 1
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LSLS R0,R0,#25 ; Check domain of interrupted thread
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BPL SVC_ContextRestore2 ; Branch if non-secure
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LDR R0,[R2,#TCB_SP_OFS] ; Load SP
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MSR PSP,R0 ; Set PSP
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BX LR ; Exit from handler
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ELSE
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LDR R0,[R2,#TCB_SM_OFS] ; Load stack memory base
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MSR PSPLIM,R0 ; Set PSPLIM
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ENDIF
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SVC_ContextRestore2
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LDR R0,[R2,#TCB_SP_OFS] ; Load SP
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ADDS R0,R0,#16 ; Adjust address
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LDMIA R0!,{R4-R7} ; Restore R8..R11
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MOV R8,R4
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MOV R9,R5
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MOV R10,R6
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MOV R11,R7
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MSR PSP,R0 ; Set PSP
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SUBS R0,R0,#32 ; Adjust address
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LDMIA R0!,{R4-R7} ; Restore R4..R7
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SVC_Exit
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BX LR ; Exit from handler
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SVC_MSP
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MRS R0,MSP ; Get MSP
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B SVC_Number
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SVC_User
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LDR R2,=osRtxUserSVC ; Load address of SVC table
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LDR R3,[R2] ; Load SVC maximum number
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CMP R1,R3 ; Check SVC number range
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BHI SVC_Exit ; Branch if out of range
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PUSH {R0,LR} ; Save SP and EXC_RETURN
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LSLS R1,R1,#2
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LDR R3,[R2,R1] ; Load address of SVC function
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MOV R12,R3
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LDMIA R0,{R0-R3} ; Load function parameters from stack
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BLX R12 ; Call service function
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POP {R2,R3} ; Restore SP and EXC_RETURN
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STR R0,[R2] ; Store function return value
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MOV LR,R3 ; Set EXC_RETURN
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BX LR ; Return from handler
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ALIGN
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ENDP
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PendSV_Handler PROC
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EXPORT PendSV_Handler
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IMPORT osRtxPendSV_Handler
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PUSH {R0,LR} ; Save EXC_RETURN
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BL osRtxPendSV_Handler ; Call osRtxPendSV_Handler
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POP {R0,R1} ; Restore EXC_RETURN
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MOV LR,R1 ; Set EXC_RETURN
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B Sys_Context
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ALIGN
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ENDP
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SysTick_Handler PROC
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EXPORT SysTick_Handler
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IMPORT osRtxTick_Handler
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PUSH {R0,LR} ; Save EXC_RETURN
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BL osRtxTick_Handler ; Call osRtxTick_Handler
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POP {R0,R1} ; Restore EXC_RETURN
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MOV LR,R1 ; Set EXC_RETURN
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B Sys_Context
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ALIGN
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ENDP
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Sys_Context PROC
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EXPORT Sys_Context
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IMPORT osRtxInfo
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IF :DEF:MPU_LOAD
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IMPORT osRtxMpuLoad
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ENDIF
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IF DOMAIN_NS = 1
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IMPORT TZ_LoadContext_S
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IMPORT TZ_StoreContext_S
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ENDIF
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LDR R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.run
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LDM R3!,{R1,R2} ; Load osRtxInfo.thread.run: curr & next
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CMP R1,R2 ; Check if thread switch is required
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BEQ Sys_ContextExit ; Branch when threads are the same
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Sys_ContextSave
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IF DOMAIN_NS = 1
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LDR R0,[R1,#TCB_TZM_OFS] ; Load TrustZone memory identifier
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CBZ R0,Sys_ContextSave1 ; Branch if there is no secure context
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PUSH {R1,R2,R3,R7} ; Save registers
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MOV R7,LR ; Get EXC_RETURN
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BL TZ_StoreContext_S ; Store secure context
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MOV LR,R7 ; Set EXC_RETURN
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POP {R1,R2,R3,R7} ; Restore registers
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MOV R0,LR ; Get EXC_RETURN
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LSLS R0,R0,#25 ; Check domain of interrupted thread
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BPL Sys_ContextSave1 ; Branch if non-secure
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MRS R0,PSP ; Get PSP
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STR R0,[R1,#TCB_SP_OFS] ; Store SP
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B Sys_ContextSave2
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ENDIF
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Sys_ContextSave1
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MRS R0,PSP ; Get PSP
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SUBS R0,R0,#32 ; Adjust address
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STR R0,[R1,#TCB_SP_OFS] ; Store SP
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STMIA R0!,{R4-R7} ; Save R4..R7
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MOV R4,R8
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MOV R5,R9
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MOV R6,R10
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MOV R7,R11
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STMIA R0!,{R4-R7} ; Save R8..R11
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Sys_ContextSave2
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MOV R0,LR ; Get EXC_RETURN
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ADDS R1,R1,#TCB_SF_OFS ; Adjust address
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STRB R0,[R1] ; Store stack frame information
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Sys_ContextSwitch
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SUBS R3,R3,#8 ; Adjust address
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STR R2,[R3] ; osRtxInfo.run: curr = next
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IF :DEF:MPU_LOAD
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PUSH {R2,R3} ; Save registers
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MOV R0,R2 ; osRtxMpuLoad parameter
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BL osRtxMpuLoad ; Load MPU for next thread
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POP {R2,R3} ; Restore registers
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ENDIF
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Sys_ContextRestore
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IF DOMAIN_NS = 1
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LDR R0,[R2,#TCB_TZM_OFS] ; Load TrustZone memory identifier
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CBZ R0,Sys_ContextRestore1 ; Branch if there is no secure context
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PUSH {R2,R3} ; Save registers
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BL TZ_LoadContext_S ; Load secure context
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POP {R2,R3} ; Restore registers
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ENDIF
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Sys_ContextRestore1
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MOV R1,R2
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ADDS R1,R1,#TCB_SF_OFS ; Adjust offset
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LDRB R0,[R1] ; Load stack frame information
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MOVS R1,#0xFF
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MVNS R1,R1 ; R1=0xFFFFFF00
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ORRS R0,R1
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MOV LR,R0 ; Set EXC_RETURN
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IF DOMAIN_NS = 1
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LSLS R0,R0,#25 ; Check domain of interrupted thread
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BPL Sys_ContextRestore2 ; Branch if non-secure
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LDR R0,[R2,#TCB_SP_OFS] ; Load SP
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MSR PSP,R0 ; Set PSP
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BX LR ; Exit from handler
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ELSE
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LDR R0,[R2,#TCB_SM_OFS] ; Load stack memory base
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MSR PSPLIM,R0 ; Set PSPLIM
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ENDIF
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Sys_ContextRestore2
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LDR R0,[R2,#TCB_SP_OFS] ; Load SP
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ADDS R0,R0,#16 ; Adjust address
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LDMIA R0!,{R4-R7} ; Restore R8..R11
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MOV R8,R4
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MOV R9,R5
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MOV R10,R6
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MOV R11,R7
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MSR PSP,R0 ; Set PSP
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SUBS R0,R0,#32 ; Adjust address
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LDMIA R0!,{R4-R7} ; Restore R4..R7
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Sys_ContextExit
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BX LR ; Exit from handler
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ALIGN
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ENDP
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END
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