204 lines
5.2 KiB
C
204 lines
5.2 KiB
C
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/***************************************************************************
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*
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* Copyright 2015-2019 BES.
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* All rights reserved. All unpublished rights reserved.
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*
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* No part of this work may be used or reproduced in any form or by any
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* means, or stored in a database or retrieval system, without prior written
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* permission of BES.
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*
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* Use of this work is governed by a license granted by BES.
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* This work contains confidential and proprietary information of
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* BES. which is protected by copyright, trade secret,
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* trademark and other intellectual property rights.
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*
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****************************************************************************/
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#include "plat_addr_map.h"
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#include "hal_pwm.h"
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#include "reg_pwm.h"
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#include "cmsis.h"
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#include "hal_cmu.h"
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#include "hal_timer.h"
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#include "hal_trace.h"
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#define PWM_SLOW_CLOCK (CONFIG_SYSTICK_HZ)
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#define PWM_FAST_CLOCK (hal_cmu_get_crystal_freq() / 2)
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#define PWM_MAX_VALUE 0xFFFF
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// Max allowed PWM freqency error in percentage
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#define PWM_MAX_FREQ_ERR_PCT 5
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static struct PWM_T * const pwm[] = {
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(struct PWM_T *)PWM_BASE,
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#ifdef CHIP_BEST2000
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(struct PWM_T *)AON_PWM_BASE,
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#endif
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};
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static const enum HAL_CMU_MOD_ID_T pwm_o_mod[] = {
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HAL_CMU_MOD_O_PWM0,
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#ifdef CHIP_BEST2000
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HAL_CMU_AON_O_PWM0,
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#endif
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};
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static const enum HAL_CMU_MOD_ID_T pwm_p_mod[] = {
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HAL_CMU_MOD_P_PWM,
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#ifdef CHIP_BEST2000
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HAL_CMU_AON_A_PWM,
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#endif
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};
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int hal_pwm_enable(enum HAL_PWM_ID_T id, const struct HAL_PWM_CFG_T *cfg)
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{
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uint32_t mod_freq;
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uint32_t load;
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uint32_t toggle;
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uint32_t lock;
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uint8_t ratio;
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uint8_t index;
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uint8_t offset;
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if (id >= HAL_PWM_ID_QTY) {
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return 1;
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}
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if (cfg->ratio > 100) {
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return 2;
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}
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if (cfg->inv && (cfg->ratio == 0 || cfg->ratio == 100)) {
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ratio = 100 - cfg->ratio;
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} else {
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ratio = cfg->ratio;
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}
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#ifdef PWM_TRY_SLOW_CLOCK
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mod_freq = PWM_SLOW_CLOCK;
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#else
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if (cfg->sleep_on) {
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mod_freq = PWM_SLOW_CLOCK;
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} else {
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mod_freq = PWM_FAST_CLOCK;
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}
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#endif
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if (ratio == 100) {
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load = PWM_MAX_VALUE;
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toggle = PWM_MAX_VALUE;
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} else if (ratio == 0) {
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load = 0;
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toggle = 0;
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} else {
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load = mod_freq / cfg->freq;
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toggle = load * ratio / 100;
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if (toggle == 0) {
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toggle = 1;
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}
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#ifdef PWM_TRY_SLOW_CLOCK
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// Check PWM frequency error in percentage
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if (!cfg->sleep_on && ABS((int)(toggle * 100 - load * ratio)) > load * PWM_MAX_FREQ_ERR_PCT) {
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mod_freq = PWM_FAST_CLOCK;
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load = mod_freq / cfg->freq;
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toggle = load * ratio / 100;
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}
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#endif
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load = PWM_MAX_VALUE + 1 - load;
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toggle = PWM_MAX_VALUE - toggle;
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}
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#ifdef CHIP_BEST2000
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if (id < HAL_PWM2_ID_0) {
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index = 0;
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offset = id - HAL_PWM_ID_0;
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} else {
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index = 1;
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offset = id - HAL_PWM2_ID_0;
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}
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#else
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index = 0;
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offset = id - HAL_PWM_ID_0;
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#endif
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if (hal_cmu_reset_get_status(pwm_o_mod[index] + offset) == HAL_CMU_RST_SET) {
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hal_cmu_clock_enable(pwm_o_mod[index] + offset);
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hal_cmu_clock_enable(pwm_p_mod[index]);
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hal_cmu_reset_clear(pwm_o_mod[index] + offset);
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hal_cmu_reset_clear(pwm_p_mod[index]);
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} else {
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pwm[index]->EN &= ~(1 << offset);
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}
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if (ratio == 0) {
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// Output 0 when disabled
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return 0;
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}
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hal_cmu_pwm_set_freq(id, mod_freq);
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lock = int_lock();
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if (offset == 0) {
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pwm[index]->LOAD01 = SET_BITFIELD(pwm[index]->LOAD01, PWM_LOAD01_0, load);
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pwm[index]->TOGGLE01 = SET_BITFIELD(pwm[index]->TOGGLE01, PWM_TOGGLE01_0, toggle);
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} else if (offset == 1) {
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pwm[index]->LOAD01 = SET_BITFIELD(pwm[index]->LOAD01, PWM_LOAD01_1, load);
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pwm[index]->TOGGLE01 = SET_BITFIELD(pwm[index]->TOGGLE01, PWM_TOGGLE01_1, toggle);
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} else if (offset == 2) {
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pwm[index]->LOAD23 = SET_BITFIELD(pwm[index]->LOAD23, PWM_LOAD23_2, load);
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pwm[index]->TOGGLE23 = SET_BITFIELD(pwm[index]->TOGGLE23, PWM_TOGGLE23_2, toggle);
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} else {
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pwm[index]->LOAD23 = SET_BITFIELD(pwm[index]->LOAD23, PWM_LOAD23_3, load);
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pwm[index]->TOGGLE23 = SET_BITFIELD(pwm[index]->TOGGLE23, PWM_TOGGLE23_3, toggle);
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}
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if (cfg->inv) {
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pwm[index]->INV |= (1 << offset);
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} else {
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pwm[index]->INV &= ~(1 << offset);
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}
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pwm[index]->EN |= (1 << offset);
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int_unlock(lock);
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return 0;
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}
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int hal_pwm_disable(enum HAL_PWM_ID_T id)
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{
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uint8_t index;
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uint8_t offset;
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if (id >= HAL_PWM_ID_QTY) {
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return 1;
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}
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#ifdef CHIP_BEST2000
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if (id < HAL_PWM2_ID_0) {
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index = 0;
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offset = id - HAL_PWM_ID_0;
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} else {
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index = 1;
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offset = id - HAL_PWM2_ID_0;
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}
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#else
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index = 0;
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offset = id - HAL_PWM_ID_0;
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#endif
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if (hal_cmu_reset_get_status(pwm_o_mod[index] + offset) == HAL_CMU_RST_SET) {
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return 0;
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}
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pwm[index]->EN &= ~(1 << offset);
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hal_cmu_reset_set(pwm_o_mod[index] + offset);
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hal_cmu_clock_disable(pwm_o_mod[index] + offset);
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if (pwm[index]->EN == 0) {
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hal_cmu_reset_set(pwm_p_mod[index]);
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hal_cmu_clock_disable(pwm_p_mod[index]);
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}
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return 0;
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}
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