356 lines
8.6 KiB
ArmAsm
356 lines
8.6 KiB
ArmAsm
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/***************************************************************************
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*
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* Copyright 2015-2019 BES.
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* All rights reserved. All unpublished rights reserved.
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*
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* No part of this work may be used or reproduced in any form or by any
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* means, or stored in a database or retrieval system, without prior written
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* permission of BES.
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*
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* Use of this work is governed by a license granted by BES.
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* This work contains confidential and proprietary information of
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* BES. which is protected by copyright, trade secret,
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* trademark and other intellectual property rights.
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*
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****************************************************************************/
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#include "plat_addr_map.h"
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#define __TTB_SIZE 0x5000
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#define __HEAP_SIZE 0x1000
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#define __STACK_SIZE 0x1000
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#define __FIQ_STACK_SIZE 0
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#define __IRQ_STACK_SIZE 0x1000
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#define __SVC_STACK_SIZE 0
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#define __ABT_STACK_SIZE 0
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#define __UND_STACK_SIZE 0
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/* TODO: Add FLASH_REGION_OFFSET if there are multiple levels of boot loaders */
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#if !defined(OTA_BOOT_SIZE) && defined(OTA_CODE_OFFSET)
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#define FLASH_REGION_BASE (FLASH_BASE + OTA_CODE_OFFSET)
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#else
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#define FLASH_REGION_BASE (FLASH_BASE)
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#endif
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#ifndef FLASH_REGION_SIZE
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#define FLASH_REGION_SIZE (FLASH_SIZE - (FLASH_REGION_BASE - FLASH_BASE))
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#endif
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#ifdef EXEC_IN_RAM
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#define EXEC_REGION RAM
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#elif defined(EXEC_IN_PSRAM)
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#define EXEC_REGION PSRAM
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#else
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#define EXEC_REGION PSRAMUHS
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#endif
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#define PSRAMUHSX_SECTION_SIZE 0x100000
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MEMORY
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{
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BOOT (rwx) : ORIGIN = DSP_BOOT_BASE, LENGTH = DSP_BOOT_SIZE
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FLASH (rx) : ORIGIN = FLASH_REGION_BASE, LENGTH = FLASH_REGION_SIZE
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RAM (rwx) : ORIGIN = DSP_RAM_BASE, LENGTH = DSP_RAM_SIZE - __TTB_SIZE
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L_TTB (rw) : ORIGIN = DSP_RAM_BASE + DSP_RAM_SIZE - __TTB_SIZE, LENGTH = __TTB_SIZE
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#ifdef PSRAM_BASE
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PSRAM (rwx) : ORIGIN = PSRAM_BASE, LENGTH = PSRAM_SIZE
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#endif
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#ifdef PSRAMUHS_BASE
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PSRAMUHS (rwx) : ORIGIN = PSRAMUHS_BASE, LENGTH = PSRAMUHS_SIZE - PSRAMUHSX_SECTION_SIZE
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PSRAMUHSX (rx) : ORIGIN = PSRAMUHSX_BASE+PSRAMUHS_SIZE-PSRAMUHSX_SECTION_SIZE, LENGTH = PSRAMUHSX_SECTION_SIZE
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#endif
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}
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/* Library configurations */
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GROUP(libgcc.a)
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#ifdef GEN_BOOT_SECTION
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ENTRY(Vectors)
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#else
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ENTRY(Reset_Handler)
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#endif
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SECTIONS
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{
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#ifdef GEN_BOOT_SECTION
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.boot :
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{
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KEEP(*(.vectors))
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} > BOOT
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/DISCARD/ :
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{
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*(*)
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}
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#else // !GEN_BOOT_SECTION
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.boot_loader :
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{
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*(.boot_loader)
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*(.boot_text_flash*)
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. = ALIGN(4);
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} > EXEC_REGION
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.sram_text :
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{
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__sram_text_data_start__ = .;
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/* memcpy.o or libc_nano.a(lib_a-memcpy.o/lib_a-memcpy-stub.o) */
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*:memcpy.o(.text*)
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*:lib_a-memcpy*.o(.text*)
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*:libc_rom.o(.text*)
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/* memset.o or libc_nano.a(lib_a-memset.o) */
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*:memset.o(.text*)
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*:lib_a-memset*.o(.text*)
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*(.boot_text_sram*)
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*(.sram_text*)
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*(.fast_text_sram*)
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. = ALIGN(4);
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} > RAM AT > EXEC_REGION
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__sram_text_data_start_load__ = LOADADDR(.sram_text);
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.sram_data :
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{
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*(.boot_data*)
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. = ALIGN(4);
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*(.sram_data*)
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. = ALIGN(4);
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} > RAM AT > EXEC_REGION
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__sram_text_data_end_load__ = LOADADDR(.sram_data) + SIZEOF(.sram_data);
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.text :
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{
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*(SVC_TABLE)
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*(.text*)
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*(.flash_text*)
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KEEP(*(.init))
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KEEP(*(.fini))
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/* .ctors */
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*crtbegin.o(.ctors)
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*crtbegin?.o(.ctors)
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*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
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*(SORT(.ctors.*))
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*(.ctors)
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/* .dtors */
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*crtbegin.o(.dtors)
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*crtbegin?.o(.dtors)
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*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
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*(SORT(.dtors.*))
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*(.dtors)
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. = ALIGN(4);
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__rodata_start = .;
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*(.rodata*)
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*(.boot_rodata*)
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__rodata_end = .;
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. = ALIGN(4);
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KEEP(*(.eh_frame*))
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KEEP(*(.build_info))
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*(.note.gnu.build-id)
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. = ALIGN(4);
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} > EXEC_REGION
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.ARM.extab :
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{
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*(.ARM.extab* .gnu.linkonce.armextab.*)
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} > EXEC_REGION
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__exidx_start = .;
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.ARM.exidx :
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{
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*(.ARM.exidx* .gnu.linkonce.armexidx.*)
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} > EXEC_REGION
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__exidx_end = .;
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.copy.table :
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{
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. = ALIGN(4);
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__copy_table_start__ = .;
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LONG (__etext)
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LONG (__data_start__)
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LONG (__data_end__ - __data_start__)
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__copy_table_end__ = .;
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} > EXEC_REGION
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.zero.table :
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{
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. = ALIGN(4);
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__zero_table_start__ = .;
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LONG (__bss_start__)
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LONG (__bss_end__ - __bss_start__)
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__zero_table_end__ = .;
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} > EXEC_REGION
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__etext = .;
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.data :
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{
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Image$$RW_DATA$$Base = .;
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__data_start__ = .;
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*(.data*)
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Image$$RW_DATA$$Limit = .;
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. = ALIGN(4);
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/* preinit data */
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PROVIDE (__preinit_array_start = .);
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KEEP(*(.preinit_array))
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PROVIDE (__preinit_array_end = .);
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. = ALIGN(4);
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/* init data */
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PROVIDE (__init_array_start = .);
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KEEP(*(SORT(.init_array.*)))
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KEEP(*(.init_array))
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PROVIDE (__init_array_end = .);
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. = ALIGN(4);
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/* finit data */
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PROVIDE (__fini_array_start = .);
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KEEP(*(SORT(.fini_array.*)))
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KEEP(*(.fini_array))
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PROVIDE (__fini_array_end = .);
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. = ALIGN(4);
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/* All data end */
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__data_end__ = .;
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} > EXEC_REGION
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.sram_bss (NOLOAD) : AT (ADDR(.sram_bss))
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{
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__sram_bss_start__ = .;
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*(.boot_bss*)
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. = ALIGN(4);
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*(.sram_bss*)
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. = ALIGN(4);
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__sram_bss_end__ = .;
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} > RAM
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#ifndef EXEC_IN_RAM
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__ram_end = .;
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#endif
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.bss ALIGN(0x400) (NOLOAD) :
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{
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Image$$ZI_DATA$$Base = .;
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__bss_start__ = .;
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*(.bss*)
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*(COMMON)
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__bss_end__ = .;
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Image$$ZI_DATA$$Limit = .;
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__end__ = .;
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end = __end__;
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} > EXEC_REGION
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#if defined(__HEAP_SIZE) && (__HEAP_SIZE > 0)
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.heap (NOLOAD) :
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{
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. = ALIGN(8);
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Image$$HEAP$$ZI$$Base = .;
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. += __HEAP_SIZE;
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Image$$HEAP$$ZI$$Limit = .;
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__HeapLimit = .;
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} > EXEC_REGION
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#endif
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.sync_flags ALIGN(0x1000) (NOLOAD) :
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{
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__sync_flags_start = .;
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*(.sync_flags*)
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. = ALIGN(0x1000);
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__sync_flags_end = .;
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} > EXEC_REGION
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#ifdef EXEC_IN_RAM
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__ram_end = .;
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#else
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__free_exec_region = ORIGIN(EXEC_REGION) + LENGTH(EXEC_REGION) - .;
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#endif
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__psramuhs_text_data_start_load__ = LOADADDR(.data) + SIZEOF(.data);
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.psramuhs_text (ORIGIN(PSRAMUHSX)) : AT (__psramuhs_text_data_start_load__)
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{
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__psramuhs_text_start = PSRAMUHSX_TO_PSRAMUHS(.);
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*(.psramuhs_text*)
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. = ALIGN(4);
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__psramuhs_text_end = PSRAMUHSX_TO_PSRAMUHS(.);
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} > PSRAMUHSX
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__psramuhs_text_data_end_load__ = __psramuhs_text_data_start_load__ + SIZEOF(.psramuhs_text);
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/* The following section MUST be the last loaded section */
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.code_start_addr : AT (__psramuhs_text_data_end_load__)
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{
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LONG(ADDR(.boot_loader));
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} > EXEC_REGION
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.stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __FIQ_STACK_SIZE - __IRQ_STACK_SIZE - __SVC_STACK_SIZE - __ABT_STACK_SIZE - __UND_STACK_SIZE) (NOLOAD) : AT (ADDR(.stack))
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{
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. = ALIGN(8);
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__StackTop = .;
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Image$$SYS_STACK$$ZI$$Base = .;
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. += __STACK_SIZE;
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Image$$SYS_STACK$$ZI$$Limit = .;
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__stack = .;
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Image$$FIQ_STACK$$ZI$$Base = .;
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. += __FIQ_STACK_SIZE;
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Image$$FIQ_STACK$$ZI$$Limit = .;
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Image$$IRQ_STACK$$ZI$$Base = .;
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. += __IRQ_STACK_SIZE;
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Image$$IRQ_STACK$$ZI$$Limit = .;
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Image$$SVC_STACK$$ZI$$Base = .;
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. += __SVC_STACK_SIZE;
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Image$$SVC_STACK$$ZI$$Limit = .;
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Image$$ABT_STACK$$ZI$$Base = .;
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. += __ABT_STACK_SIZE;
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Image$$ABT_STACK$$ZI$$Limit = .;
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Image$$UND_STACK$$ZI$$Base = .;
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. += __UND_STACK_SIZE;
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Image$$UND_STACK$$ZI$$Limit = .;
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} > RAM
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__free_ram = ADDR(.stack) - __ram_end;
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#ifdef EXEC_IN_RAM
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__free_exec_region = __free_ram;
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#endif
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.ttb_l2 (NOLOAD) :
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{
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Image$$TTB$$ZI$$Base = .;
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*(.ttb_l2)
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} > L_TTB
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.ttb_l1 (NOLOAD) :
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{
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*(.ttb_l1)
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Image$$TTB$$ZI$$Limit = .;
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} > L_TTB
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__free_ttb = ORIGIN(L_TTB) + LENGTH(L_TTB) - .;
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#endif // !GEN_BOOT_SECTION
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}
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