337 lines
15 KiB
C
337 lines
15 KiB
C
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/***************************************************************************
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*
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* Copyright 2015-2020 BES.
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* All rights reserved. All unpublished rights reserved.
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*
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* No part of this work may be used or reproduced in any form or by any
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* means, or stored in a database or retrieval system, without prior written
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* permission of BES.
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*
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* Use of this work is governed by a license granted by BES.
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* This work contains confidential and proprietary information of
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* BES. which is protected by copyright, trade secret,
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* trademark and other intellectual property rights.
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*
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****************************************************************************/
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#ifndef __REG_SEC_ENG_H__
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#define __REG_SEC_ENG_H__
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#include "plat_types.h"
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#include "plat_addr_map.h"
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#define SE_ADEC_BASE (SEC_ENG_BASE + 0x0400)
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#define SE_DMACFG_BASE (SEC_ENG_BASE + 0x0800)
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#define SE_ACB_BASE (SEC_ENG_BASE + 0x0C00)
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#define SE_CRYPT_BASE (SEC_ENG_BASE + 0x1000)
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#define SE_ECP_BASE (SEC_ENG_BASE + 0x1400)
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#define SE_HASH_BASE (SEC_ENG_BASE + 0x1800)
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#define SE_SCRATCH_BASE (SEC_ENG_BASE + 0x1C00)
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#define SE_ZMODP_BASE (SEC_ENG_BASE + 0x2000)
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#define SE_MCT_BASE (SEC_ENG_BASE + 0x2400)
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#define SE_OTP_BASE (SEC_ENG_BASE + 0x2800)
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#define SE_EBG_BASE (SEC_ENG_BASE + 0x2C00)
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#define SE_DMA_RX_FIFO_DEPTH 32
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#define SE_DMA_TX_FIFO_DEPTH 16
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struct SE_ADEC_T {
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__IO uint32_t ADEC_CTRL; // 0x000
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__IO uint32_t ADEC_CTRL2; // 0x004
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__IO uint32_t RESERVED_00C; // 0x008
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__IO uint32_t ADEC_INT; // 0x00C
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__IO uint32_t ADEC_INT_MSK; // 0x010
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__IO uint32_t ADEC_ERR_ADR; // 0x014
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__IO uint32_t RESERVED_018; // 0x018
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};
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struct SE_DMACFG_T {
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__IO uint32_t DMA_CTRL; // 0x000
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__IO uint32_t DMA_TDL; // 0x004
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__IO uint32_t DMA_RDL; // 0x008
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__IO uint32_t DMA_STATUS; // 0x00C
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__IO uint32_t DMA_TXFIFO; // 0x010
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__IO uint32_t DMA_RXFIFO; // 0x014
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__IO uint32_t DMA_FIFOCLR; // 0x018
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};
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struct SE_ACB_T {
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__IO uint32_t ACB_CTRL; // 0x000
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};
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struct SE_CRYPT_T {
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__IO uint32_t AES_CFG; // 0x000
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__IO uint32_t AES_CTRL; // 0x004
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__IO uint32_t AES_CMD; // 0x008
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__IO uint32_t AES_STATUS; // 0x00C
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__IO uint32_t AES_INTRPT; // 0x010
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__IO uint32_t AES_INTRPT_SRC_EN; // 0x014
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__IO uint32_t AES_STREAM_SIZE; // 0x018
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__IO uint32_t DES_CFG; // 0x01C
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__IO uint32_t DES_CTRL; // 0x020
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__IO uint32_t DES_CMD; // 0x024
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__IO uint32_t DES_STATUS; // 0x028
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__IO uint32_t DES_INTRPT; // 0x02C
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__IO uint32_t DES_INTRPT_SRC_EN; // 0x030
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__IO uint32_t DES_STREAM_SIZE; // 0x034
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__IO uint32_t RC4_CFG; // 0x038
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__IO uint32_t RC4_CTRL; // 0x03C
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__IO uint32_t RC4_CMD; // 0x040
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__IO uint32_t RC4_STATUS; // 0x044
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__IO uint32_t RC4_INTRPT; // 0x048
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__IO uint32_t RC4_INTRPT_SRC_EN; // 0x04C
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__IO uint32_t RC4_STREAM_SIZE; // 0x050
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__IO uint32_t RC4_INDEX; // 0x054
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__IO uint32_t KEY2[8]; // 0x058
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__IO uint32_t KEY1[8]; // 0x078
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__IO uint32_t IV[4]; // 0x098
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__IO uint32_t ENGINE_SELECT; // 0x0A8
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};
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struct SE_ECP_T {
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__IO uint32_t ECP_CFG; // 0x000
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__IO uint32_t ECP_CTRL; // 0x004
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__IO uint32_t ECP_CMD; // 0x008
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__IO uint32_t ECP_INTRPT; // 0x00C
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__IO uint32_t ECP_STATUS; // 0x010
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__IO uint32_t ECP_INTRPT_MASK; // 0x014
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__IO uint32_t ECP_SRAM[136]; // 0x018
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};
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struct SE_HASH_T {
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__IO uint32_t HASH_CFG; // 0x000
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__IO uint32_t HASH_CTRL; // 0x004
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__IO uint32_t HASH_CMD; // 0x008
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__IO uint32_t HASH_STATUS; // 0x00C
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__IO uint32_t HASH_SEG_SIZE; // 0x010
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__IO uint32_t RESERVED_014; // 0x014
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__IO uint32_t HASH_MSG_SIZE_L; // 0x018
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__IO uint32_t HASH_MSG_SIZE_H; // 0x01C
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__IO uint32_t HASH_CTX[8]; // 0x020
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__IO uint32_t HASH_CTX_H[8]; // 0x040
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__IO uint32_t HMAC_CTX[8]; // 0x060
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__IO uint32_t HMAC_CTX_H[8]; // 0x080
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__IO uint32_t HMAC_KEY_LEN; // 0x0A0
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__IO uint32_t HMAC_KEY[32]; // 0x0A4
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};
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struct SE_SCRATCH_T {
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__IO uint32_t SP_CTRL; // 0x000
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__IO uint32_t SP_STATUS; // 0x004
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__IO uint32_t SP_CPU_WR_ADDR; // 0x008
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__IO uint32_t SP_CPU_WR_DATA; // 0x00C
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__IO uint32_t SP_CPU_RD_ADDR; // 0x010
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__IO uint32_t SP_CPU_RD_DATA; // 0x014
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__IO uint32_t SP_SET_WR_ADDR; // 0x018
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__IO uint32_t SP_SET_RD_ADDR; // 0x01C
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};
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struct SE_ZMODP_T {
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__IO uint32_t ZMODP_CFG; // 0x000
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__IO uint32_t ZMODP_CTRL; // 0x004
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__IO uint32_t ZMODP_CMD; // 0x008
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__IO uint32_t ZMODP_STATUS; // 0x00C
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__IO uint32_t ZMODP_INTRPT_SRC; // 0x010
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__IO uint32_t ZMODP_INTRPT_SRC_EN; // 0x014
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__IO uint32_t ZMODP_MEM[196]; // 0x018
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};
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struct SE_MCT_T {
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__IO uint32_t MCT_CTRL; // 0x000
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__IO uint32_t MCT_CMD; // 0x004
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__IO uint32_t MCT_STATUS; // 0x008
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__IO uint32_t MCT_INTRPT; // 0x00C
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__IO uint32_t MCT_INTRPT_MASK; // 0x010
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__IO uint32_t MCT_VAL[5]; // 0x014
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};
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struct SE_OTP_T {
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__IO uint32_t OTP[16]; // 0x000
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__IO uint32_t RESERVED_040[18]; // 0x040
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__IO uint32_t CRYPT_KEY_CNTR; // 0x088
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__IO uint32_t EBG_RNG_CTRL; // 0x08C
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};
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struct SE_EBG_T {
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__IO uint32_t EBG_CTRL; // 0x000
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__IO uint32_t EBG_ENTROPY; // 0x004
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};
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// ADEC_CTRL
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#define ADEC_CTRL_CLK_EN_15_0_SHIFT 16
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#define ADEC_CTRL_CLK_EN_15_0_MASK (0xFFFF << ADEC_CTRL_CLK_EN_15_0_SHIFT)
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#define ADEC_CTRL_CLK_EN_15_0(n) BITFIELD_VAL(ADEC_CTRL_CLK_EN_15_0, n)
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#define ADEC_CTRL_RST_15_0_SHIFT 0
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#define ADEC_CTRL_RST_15_0_MASK (0xFFFF << ADEC_CTRL_RST_15_0_SHIFT)
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#define ADEC_CTRL_RST_15_0(n) BITFIELD_VAL(ADEC_CTRL_RST_15_0, n)
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// ADEC_CTRL2
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#define ADEC_CTRL2_CLK_EN_20_16_SHIFT 16
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#define ADEC_CTRL2_CLK_EN_20_16_MASK (0x1F << ADEC_CTRL2_CLK_EN_20_16_SHIFT)
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#define ADEC_CTRL2_CLK_EN_20_16(n) BITFIELD_VAL(ADEC_CTRL2_CLK_EN_20_16, n)
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#define ADEC_CTRL2_RST_20_16_SHIFT 0
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#define ADEC_CTRL2_RST_20_16_MASK (0x1F << ADEC_CTRL2_RST_20_16_SHIFT)
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#define ADEC_CTRL2_RST_20_16(n) BITFIELD_VAL(ADEC_CTRL2_RST_20_16, n)
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// DMA_CTRL
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#define DMA_CTRL_RX_DMA_SINGLE_DIS (1 << 3)
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#define DMA_CTRL_TX_DMA_SINGLE_DIS (1 << 2)
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#define DMA_CTRL_RX_DMA_EN (1 << 1)
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#define DMA_CTRL_TX_DMA_EN (1 << 0)
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// DMA_FIFOCLR
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#define DMA_FIFOCLR_RXFIFO_CLR (1 << 1)
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#define DMA_FIFOCLR_TXFIFO_CLR (1 << 0)
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// DMA_STATUS
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#define DMA_STATUS_RX_VALID_CNT_SHIFT 10
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#define DMA_STATUS_RX_VALID_CNT_MASK (0x1F << DMA_STATUS_RX_VALID_CNT_SHIFT)
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#define DMA_STATUS_RX_VALID_CNT(n) BITFIELD_VAL(DMA_STATUS_RX_VALID_CNT, n)
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#define DMA_STATUS_RX_FULL (1 << 9)
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#define DMA_STATUS_RX_EMPTY (1 << 7)
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#define DMA_STATUS_TX_VALID_CNT_SHIFT 2
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#define DMA_STATUS_TX_VALID_CNT_MASK (0x1F << DMA_STATUS_TX_VALID_CNT_SHIFT)
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#define DMA_STATUS_TX_VALID_CNT(n) BITFIELD_VAL(DMA_STATUS_TX_VALID_CNT, n)
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#define DMA_STATUS_TX_FULL (1 << 1)
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#define DMA_STATUS_TX_EMPTY (1 << 0)
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// ACB_CTRL
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#define ACB_CTRL_RSVD_31_11_SHIFT 11
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#define ACB_CTRL_RSVD_31_11_MASK (0x1FFFFF << ACB_CTRL_RSVD_31_11_SHIFT)
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#define ACB_CTRL_RSVD_31_11(n) BITFIELD_VAL(ACB_CTRL_RSVD_31_11, n)
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#define ACB_CTRL_GROUPB_SELECT_SHIFT 8
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#define ACB_CTRL_GROUPB_SELECT_MASK (0x7 << ACB_CTRL_GROUPB_SELECT_SHIFT)
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#define ACB_CTRL_GROUPB_SELECT(n) BITFIELD_VAL(ACB_CTRL_GROUPB_SELECT, n)
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#define ACB_CTRL_RSVD_7 (1 << 7)
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#define ACB_CTRL_GROUPA_SELECT_SHIFT 4
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#define ACB_CTRL_GROUPA_SELECT_MASK (0x7 << ACB_CTRL_GROUPA_SELECT_SHIFT)
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#define ACB_CTRL_GROUPA_SELECT(n) BITFIELD_VAL(ACB_CTRL_GROUPA_SELECT, n)
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#define ACB_CTRL_RSVD_3 (1 << 3)
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#define ACB_CTRL_WR_CB_CTRL (1 << 2)
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#define ACB_CTRL_RSVD_1 (1 << 1)
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#define ACB_CTRL_RD_CB_CTRL (1 << 0)
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// AES_CFG
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#define AES_CFG_RSVD_31_17_SHIFT 17
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#define AES_CFG_RSVD_31_17_MASK (0x7FFF << AES_CFG_RSVD_31_17_SHIFT)
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#define AES_CFG_RSVD_31_17(n) BITFIELD_VAL(AES_CFG_RSVD_31_17, n)
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#define AES_CFG_CTS_MODE (1 << 16)
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#define AES_CFG_RSVD (1 << 15)
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#define AES_CFG_MODULAR_SHIFT 8
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#define AES_CFG_MODULAR_MASK (0x7F << AES_CFG_MODULAR_SHIFT)
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#define AES_CFG_MODULAR(n) BITFIELD_VAL(AES_CFG_MODULAR, n)
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#define AES_CFG_RSVD_7 (1 << 7)
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#define AES_CFG_RKEY (1 << 6)
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#define AES_CFG_MODE_SHIFT 3
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#define AES_CFG_MODE_MASK (0x7 << AES_CFG_MODE_SHIFT)
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#define AES_CFG_MODE(n) BITFIELD_VAL(AES_CFG_MODE, n)
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#define AES_CFG_KEYLEN_SHIFT 1
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#define AES_CFG_KEYLEN_MASK (0x3 << AES_CFG_KEYLEN_SHIFT)
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#define AES_CFG_KEYLEN(n) BITFIELD_VAL(AES_CFG_KEYLEN, n)
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#define AES_CFG_DECRYPT (1 << 0)
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// AES_CTRL
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#define AES_CTRL_RSVD_31_3_SHIFT 3
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#define AES_CTRL_RSVD_31_3_MASK (0x1FFFFFFF << AES_CTRL_RSVD_31_3_SHIFT)
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#define AES_CTRL_RSVD_31_3(n) BITFIELD_VAL(AES_CTRL_RSVD_31_3, n)
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#define AES_CTRL_OUTPUTBLOCK (1 << 2)
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#define AES_CTRL_RESUME (1 << 1)
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#define AES_CTRL_RESET (1 << 0)
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// AES_CMD
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#define AES_CMD_RSVD_31_1_SHIFT 1
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#define AES_CMD_RSVD_31_1_MASK (0x7FFFFFFF << AES_CMD_RSVD_31_1_SHIFT)
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#define AES_CMD_RSVD_31_1(n) BITFIELD_VAL(AES_CMD_RSVD_31_1, n)
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#define AES_CMD_START (1 << 0)
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// AES_STATUS
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#define AES_STATUS_RSVD_31_5_SHIFT 5
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#define AES_STATUS_RSVD_31_5_MASK (0x7FFFFFF << AES_STATUS_RSVD_31_5_SHIFT)
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#define AES_STATUS_RSVD_31_5(n) BITFIELD_VAL(AES_STATUS_RSVD_31_5, n)
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#define AES_STATUS_STATE_SHIFT 1
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#define AES_STATUS_STATE_MASK (0xF << AES_STATUS_STATE_SHIFT)
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#define AES_STATUS_STATE(n) BITFIELD_VAL(AES_STATUS_STATE, n)
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#define AES_STATUS_BUSY (1 << 0)
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// AES_INTRPT
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#define AES_INTRPT_RSVD_31_3_SHIFT 3
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#define AES_INTRPT_RSVD_31_3_MASK (0x1FFFFFFF << AES_INTRPT_RSVD_31_3_SHIFT)
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#define AES_INTRPT_RSVD_31_3(n) BITFIELD_VAL(AES_INTRPT_RSVD_31_3, n)
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#define AES_INTRPT_ERROR2 (1 << 2)
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#define AES_INTRPT_ERROR1 (1 << 1)
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#define AES_INTRPT_DONE (1 << 0)
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// AES_INTRPT_SRC_EN
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#define AES_INTRPT_SRC_EN_RSVD_31_3_SHIFT 3
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#define AES_INTRPT_SRC_EN_RSVD_31_3_MASK (0x1FFFFFFF << AES_INTRPT_SRC_EN_RSVD_31_3_SHIFT)
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#define AES_INTRPT_SRC_EN_RSVD_31_3(n) BITFIELD_VAL(AES_INTRPT_SRC_EN_RSVD_31_3, n)
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#define AES_INTRPT_SRC_EN_ERROR2 (1 << 2)
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#define AES_INTRPT_SRC_EN_ERROR1 (1 << 1)
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#define AES_INTRPT_SRC_EN_DONE (1 << 0)
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// ENGINE_SELECT
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#define ENGINE_SELECT_RSVD_31_2_SHIFT 2
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#define ENGINE_SELECT_RSVD_31_2_MASK (0x3FFFFFFF << ENGINE_SELECT_RSVD_31_2_SHIFT)
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#define ENGINE_SELECT_RSVD_31_2(n) BITFIELD_VAL(ENGINE_SELECT_RSVD_31_2, n)
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#define ENGINE_SELECT_SELECT_SHIFT 0
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#define ENGINE_SELECT_SELECT_MASK (0x3 << ENGINE_SELECT_SELECT_SHIFT)
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#define ENGINE_SELECT_SELECT(n) BITFIELD_VAL(ENGINE_SELECT_SELECT, n)
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// HASH_CFG
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#define HASH_CFG_RSVD_31_5_SHIFT 5
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#define HASH_CFG_RSVD_31_5_MASK (0x7FFFFFF << HASH_CFG_RSVD_31_5_SHIFT)
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#define HASH_CFG_RSVD_31_5(n) BITFIELD_VAL(HASH_CFG_RSVD_31_5, n)
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#define HASH_CFG_OUTPUT_DATA_MODE (1 << 4)
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#define HASH_CFG_HASH_MODE (1 << 3)
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#define HASH_CFG_ALG_SELECT_SHIFT 0
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#define HASH_CFG_ALG_SELECT_MASK (0x7 << HASH_CFG_ALG_SELECT_SHIFT)
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#define HASH_CFG_ALG_SELECT(n) BITFIELD_VAL(HASH_CFG_ALG_SELECT, n)
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// HASH_CTRL
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#define HASH_CTRL_RSVD_31_4_SHIFT 4
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#define HASH_CTRL_RSVD_31_4_MASK (0xFFFFFFF << HASH_CTRL_RSVD_31_4_SHIFT)
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#define HASH_CTRL_RSVD_31_4(n) BITFIELD_VAL(HASH_CTRL_RSVD_31_4, n)
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#define HASH_CTRL_RESET (1 << 3)
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#define HASH_CTRL_HW_PADDING (1 << 2)
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#define HASH_CTRL_HASH_OP_MODE_SHIFT 0
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#define HASH_CTRL_HASH_OP_MODE_MASK (0x3 << HASH_CTRL_HASH_OP_MODE_SHIFT)
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#define HASH_CTRL_HASH_OP_MODE(n) BITFIELD_VAL(HASH_CTRL_HASH_OP_MODE, n)
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// HASH_CMD
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#define HASH_CMD_RSVD_31_1_SHIFT 1
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#define HASH_CMD_RSVD_31_1_MASK (0x7FFFFFFF << HASH_CMD_RSVD_31_1_SHIFT)
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#define HASH_CMD_RSVD_31_1(n) BITFIELD_VAL(HASH_CMD_RSVD_31_1, n)
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#define HASH_CMD_START (1 << 0)
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// HASH_STATUS
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#define HASH_STATUS_RSVD_31_4_SHIFT 4
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#define HASH_STATUS_RSVD_31_4_MASK (0xFFFFFFF << HASH_STATUS_RSVD_31_4_SHIFT)
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#define HASH_STATUS_RSVD_31_4(n) BITFIELD_VAL(HASH_STATUS_RSVD_31_4, n)
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#define HASH_STATUS_HMAC_SM_BUSY (1 << 3)
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#define HASH_STATUS_XFER_SM_BUSY (1 << 2)
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#define HASH_STATUS_HASH_BUSY (1 << 1)
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#define HASH_STATUS_HASH_DONE (1 << 0)
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// HMAC_KEY_LEN
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#define HMAC_KEY_LEN_RSVD_31_8_SHIFT 8
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#define HMAC_KEY_LEN_RSVD_31_8_MASK (0xFFFFFF << HMAC_KEY_LEN_RSVD_31_8_SHIFT)
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#define HMAC_KEY_LEN_RSVD_31_8(n) BITFIELD_VAL(HMAC_KEY_LEN_RSVD_31_8, n)
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#define HMAC_KEY_LEN_LEN_SHIFT 0
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#define HMAC_KEY_LEN_LEN_MASK (0xFF << HMAC_KEY_LEN_LEN_SHIFT)
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#define HMAC_KEY_LEN_LEN(n) BITFIELD_VAL(HMAC_KEY_LEN_LEN, n)
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// CRYPT_KEY_CNTR
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#define CRYPT_KEY_CNTR_KEY_SEL (1 << 2)
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#define CRYPT_KEY_CNTR_DEV1_ENCRYPT (1 << 1)
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#define CRYPT_KEY_CNTR_DEV0_ENCRYPT (1 << 0)
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// EBG_RNG_CTRL
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#define EBG_RNG_CTRL_RNG_SEL (1 << 16)
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#define EBG_RNG_CTRL_SEED_SHIFT 0
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#define EBG_RNG_CTRL_SEED_MASK (0xFFFF << EBG_RNG_CTRL_SEED_SHIFT)
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#define EBG_RNG_CTRL_SEED(n) BITFIELD_VAL(EBG_RNG_CTRL_SEED, n)
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#endif
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