249 lines
11 KiB
C
249 lines
11 KiB
C
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/***************************************************************************
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*
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* Copyright 2015-2019 BES.
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* All rights reserved. All unpublished rights reserved.
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*
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* No part of this work may be used or reproduced in any form or by any
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* means, or stored in a database or retrieval system, without prior written
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* permission of BES.
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*
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* Use of this work is governed by a license granted by BES.
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* This work contains confidential and proprietary information of
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* BES. which is protected by copyright, trade secret,
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* trademark and other intellectual property rights.
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*
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****************************************************************************/
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#ifndef __REG_I2SIP_H_
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#define __REG_I2SIP_H_
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#include "plat_types.h"
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#define I2SIP_FIFO_DEPTH 8
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#define I2SIP_CHAN_REG_SIZE 0x40
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#define I2SIP_CHAN_REG(c, r) (c * I2SIP_CHAN_REG_SIZE + r)
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/* i2sip register */
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/* enable register */
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#define I2SIP_ENABLE_REG_REG_OFFSET 0x0
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#define I2SIP_ENABLE_REG_I2S_ENABLE_SHIFT (0)
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#define I2SIP_ENABLE_REG_I2S_ENABLE_MASK ((0x1)<<I2SIP_ENABLE_REG_I2S_ENABLE_SHIFT)
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#ifndef CHIP_BEST1000
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#define I2SIP_ENABLE_REG_SLAVE_MODE_SHIFT (1)
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#define I2SIP_ENABLE_REG_SLAVE_MODE_MASK (1 << I2SIP_ENABLE_REG_SLAVE_MODE_SHIFT)
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#endif
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#define I2SIP_ENABLE_REG_SPDIF_ENABLE_SHIFT (8)
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#define I2SIP_ENABLE_REG_SPDIF_ENABLE_MASK ((0x1)<<I2SIP_ENABLE_REG_SPDIF_ENABLE_SHIFT)
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/* recv block enable register */
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#define I2SIP_RX_BLOCK_ENABLE_REG_REG_OFFSET 0x4
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#define I2SIP_RX_BLOCK_ENABLE_REG_ENABLE_SHIFT (0)
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#define I2SIP_RX_BLOCK_ENABLE_REG_ENABLE_MASK ((0x1)<<I2SIP_RX_BLOCK_ENABLE_REG_ENABLE_SHIFT)
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/* send block enable register */
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#define I2SIP_TX_BLOCK_ENABLE_REG_REG_OFFSET 0x8
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#define I2SIP_TX_BLOCK_ENABLE_REG_ENABLE_SHIFT (0)
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#define I2SIP_TX_BLOCK_ENABLE_REG_ENABLE_MASK ((0x1)<<I2SIP_TX_BLOCK_ENABLE_REG_ENABLE_SHIFT)
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/* clk gen enable register */
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#define I2SIP_CLK_GEN_ENABLE_REG_REG_OFFSET 0xc
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#define I2SIP_CLK_GEN_ENABLE_REG_ENABLE_SHIFT (0)
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#define I2SIP_CLK_GEN_ENABLE_REG_ENABLE_MASK ((0x1)<<I2SIP_CLK_GEN_ENABLE_REG_ENABLE_SHIFT)
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/* clk config register */
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#define I2SIP_CLK_CFG_REG_OFFSET 0x10
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#define I2SIP_CLK_CFG_WSS_SHIFT (3)
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#define I2SIP_CLK_CFG_WSS_MASK ((0x3)<<I2SIP_CLK_CFG_WSS_SHIFT)
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#define I2SIP_CLK_CFG_WSS_VAL_16CYCLE 0
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#define I2SIP_CLK_CFG_WSS_VAL_24CYCLE 1
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#define I2SIP_CLK_CFG_WSS_VAL_32CYCLE 2
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#define I2SIP_CLK_CFG_SCLK_GATE_SHIFT (0)
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#define I2SIP_CLK_CFG_SCLK_GATE_MASK ((0x7)<<I2SIP_CLK_CFG_SCLK_GATE_SHIFT)
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#define I2SIP_CLK_CFG_SCLK_GATE_VAL_NO_GATE 0
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#define I2SIP_CLK_CFG_SCLK_GATE_VAL_12_GATE 1
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#define I2SIP_CLK_CFG_SCLK_GATE_VAL_16_GATE 2
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#define I2SIP_CLK_CFG_SCLK_GATE_VAL_20_GATE 3
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#define I2SIP_CLK_CFG_SCLK_GATE_VAL_24_GATE 4
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/* recv block fifo reset register */
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#define I2SIP_RX_BLOCK_FIFO_RESET_REG_OFFSET 0x14
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#define I2SIP_RX_BLOCK_FIFO_RESET_RESET_SHIFT (0)
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#define I2SIP_RX_BLOCK_FIFO_RESET_RESET_MASK ((0x1)<<I2SIP_RX_BLOCK_FIFO_RESET_RESET_SHIFT)
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/* send block fifo reset register */
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#define I2SIP_TX_BLOCK_FIFO_RESET_REG_OFFSET 0x18
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#define I2SIP_TX_BLOCK_FIFO_RESET_RESET_SHIFT (0)
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#define I2SIP_TX_BLOCK_FIFO_RESET_RESET_MASK ((0x1)<<I2SIP_TX_BLOCK_FIFO_RESET_RESET_SHIFT)
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/* left recv buffer register */
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#define I2SIP_LEFT_RX_BUFF_REG_OFFSET(c) I2SIP_CHAN_REG(c, 0x20)
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/* left send buffer register */
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#define I2SIP_LEFT_TX_BUFF_REG_OFFSET(c) I2SIP_CHAN_REG(c, 0x20)
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/* right recv buffer register */
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#define I2SIP_RIGHT_RX_BUFF_REG_OFFSET(c) I2SIP_CHAN_REG(c, 0x24)
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/* right send buffer register */
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#define I2SIP_RIGHT_TX_BUFF_REG_OFFSET(c) I2SIP_CHAN_REG(c, 0x24)
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/* channel 0 */
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/* recv enable register */
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#define I2SIP_RX_ENABLE_REG_OFFSET(c) I2SIP_CHAN_REG(c, 0x28)
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#define I2SIP_RX_ENABLE_ENABLE_SHIFT (0)
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#define I2SIP_RX_ENABLE_ENABLE_MASK ((0x1)<<I2SIP_RX_ENABLE_ENABLE_SHIFT)
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/* send enable register */
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#define I2SIP_TX_ENABLE_REG_OFFSET(c) I2SIP_CHAN_REG(c, 0x2c)
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#define I2SIP_TX_ENABLE_ENABLE_SHIFT (0)
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#define I2SIP_TX_ENABLE_ENABLE_MASK ((0x1)<<I2SIP_TX_ENABLE_ENABLE_SHIFT)
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/* recv config register */
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#define I2SIP_RX_CFG_REG_OFFSET(c) I2SIP_CHAN_REG(c, 0x30)
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#define I2SIP_RX_CFG_WLEN_SHIFT (0)
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#define I2SIP_RX_CFG_WLEN_MASK ((0x7)<<I2SIP_RX_CFG_WLEN_SHIFT)
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#define I2SIP_RX_CFG_WLEN_VAL_IGNORE 0
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#define I2SIP_RX_CFG_WLEN_VAL_12BIT 1
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#define I2SIP_RX_CFG_WLEN_VAL_16BIT 2
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#define I2SIP_RX_CFG_WLEN_VAL_20BIT 3
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#define I2SIP_RX_CFG_WLEN_VAL_24BIT 4
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#define I2SIP_RX_CFG_WLEN_VAL_32BIT 5
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/* send config register */
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#define I2SIP_TX_CFG_REG_OFFSET(c) I2SIP_CHAN_REG(c, 0x34)
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#define I2SIP_TX_CFG_WLEN_SHIFT (0)
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#define I2SIP_TX_CFG_WLEN_MASK ((0x7)<<I2SIP_TX_CFG_WLEN_SHIFT)
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#define I2SIP_TX_CFG_WLEN_VAL_IGNORE 0
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#define I2SIP_TX_CFG_WLEN_VAL_12BIT 1
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#define I2SIP_TX_CFG_WLEN_VAL_16BIT 2
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#define I2SIP_TX_CFG_WLEN_VAL_20BIT 3
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#define I2SIP_TX_CFG_WLEN_VAL_24BIT 4
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#define I2SIP_TX_CFG_WLEN_VAL_32BIT 5
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/* recv or send config register */
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#define I2SIP_CFG_WLEN_VAL_IGNORE 0
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#define I2SIP_CFG_WLEN_VAL_12BIT 1
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#define I2SIP_CFG_WLEN_VAL_16BIT 2
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#define I2SIP_CFG_WLEN_VAL_20BIT 3
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#define I2SIP_CFG_WLEN_VAL_24BIT 4
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#define I2SIP_CFG_WLEN_VAL_32BIT 5
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/* int status register */
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#define I2SIP_INT_STATUS_REG_OFFSET(c) I2SIP_CHAN_REG(c, 0x38)
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#define I2SIP_INT_STATUS_TX_FIFO_OVER_SHIFT (5)
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#define I2SIP_INT_STATUS_TX_FIFO_OVER_MASK ((0x1)<<I2SIP_INT_STATUS_TX_FIFO_OVER_SHIFT)
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#define I2SIP_INT_STATUS_TX_FIFO_EMPTY_SHIFT (4)
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#define I2SIP_INT_STATUS_TX_FIFO_EMPTY_MASK ((0x1)<<I2SIP_INT_STATUS_TX_FIFO_EMPTY_SHIFT)
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#define I2SIP_INT_STATUS_RX_FIFO_OVER_SHIFT (1)
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#define I2SIP_INT_STATUS_RX_FIFO_OVER_MASK ((0x1)<<I2SIP_INT_STATUS_RX_FIFO_OVER_SHIFT)
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#define I2SIP_INT_STATUS_RX_FIFO_DA_SHIFT (0)
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#define I2SIP_INT_STATUS_RX_FIFO_DA_MASK ((0x1)<<I2SIP_INT_STATUS_RX_FIFO_DA_SHIFT)
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/* int mask register */
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#define I2SIP_INT_MASK_REG_OFFSET(c) I2SIP_CHAN_REG(c, 0x3c)
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#define I2SIP_INT_MASK_TX_FIFO_OVER_SHIFT (5)
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#define I2SIP_INT_MASK_TX_FIFO_OVER_MASK ((0x1)<<I2SIP_INT_MASK_TX_FIFO_OVER_SHIFT)
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#define I2SIP_INT_MASK_TX_FIFO_EMPTY_SHIFT (4)
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#define I2SIP_INT_MASK_TX_FIFO_EMPTY_MASK ((0x1)<<I2SIP_INT_MASK_TX_FIFO_EMPTY_SHIFT)
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#define I2SIP_INT_MASK_RX_FIFO_OVER_SHIFT (1)
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#define I2SIP_INT_MASK_RX_FIFO_OVER_MASK ((0x1)<<I2SIP_INT_MASK_RX_FIFO_OVER_SHIFT)
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#define I2SIP_INT_MASK_RX_FIFO_DA_SHIFT (0)
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#define I2SIP_INT_MASK_RX_FIFO_DA_MASK ((0x1)<<I2SIP_INT_MASK_RX_FIFO_DA_SHIFT)
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#define I2SIP_INT_MASK_ALL \
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(I2SIP_INT_MASK_TX_FIFO_OVER_MASK|I2SIP_INT_MASK_TX_FIFO_EMPTY_MASK|I2SIP_INT_MASK_RX_FIFO_OVER_MASK|I2SIP_INT_MASK_RX_FIFO_DA_MASK)
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#define I2SIP_INT_UNMASK_ALL 0
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/* clr recv over flow register */
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#define I2SIP_CLR_RX_OVER_FLOW_REG_OFFSET(c) I2SIP_CHAN_REG(c, 0x40)
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#define I2SIP_CLR_RX_OVER_FLOW_CLR_SHIFT (0)
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#define I2SIP_CLR_RX_OVER_FLOW_CLR_MASK ((0x1)<<I2SIP_CLR_RX_OVER_FLOW_CLR_SHIFT)
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/* clr send over flow register */
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#define I2SIP_CLR_TX_OVER_FLOW_REG_OFFSET(c) I2SIP_CHAN_REG(c, 0x44)
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#define I2SIP_CLR_TX_OVER_FLOW_CLR_SHIFT (0)
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#define I2SIP_CLR_TX_OVER_FLOW_CLR_MASK ((0x1)<<I2SIP_CLR_TX_OVER_FLOW_CLR_SHIFT)
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/* recv fifo config register */
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#define I2SIP_RX_FIFO_CFG_REG_OFFSET(c) I2SIP_CHAN_REG(c, 0x48)
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#define I2SIP_RX_FIFO_CFG_LEVEL_SHIFT (0)
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#define I2SIP_RX_FIFO_CFG_LEVEL_MASK ((0xf)<<I2SIP_RX_FIFO_CFG_LEVEL_SHIFT)
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/* send fifo config register */
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#define I2SIP_TX_FIFO_CFG_REG_OFFSET(c) I2SIP_CHAN_REG(c, 0x4c)
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#define I2SIP_TX_FIFO_CFG_LEVEL_SHIFT (0)
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#define I2SIP_TX_FIFO_CFG_LEVEL_MASK ((0xf)<<I2SIP_TX_FIFO_CFG_LEVEL_SHIFT)
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/* recv fifo flush register */
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#define I2SIP_RX_FIFO_FLUSH_REG_OFFSET(c) I2SIP_CHAN_REG(c, 0x50)
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#define I2SIP_RX_FIFO_FLUSH_SHIFT (0)
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#define I2SIP_RX_FIFO_FLUSH_MASK ((0x1)<<I2SIP_RX_FIFO_FLUSH_SHIFT)
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/* send fifo flush register */
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#define I2SIP_TX_FIFO_FLUSH_REG_OFFSET(c) I2SIP_CHAN_REG(c, 0x54)
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#define I2SIP_TX_FIFO_FLUSH_SHIFT (0)
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#define I2SIP_TX_FIFO_FLUSH_MASK ((0x1)<<I2SIP_TX_FIFO_FLUSH_SHIFT)
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/* dma ctrl register */
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#ifdef CHIP_BEST1000
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#define I2SIP_DMA_CTRL_REG_OFFSET 0x58
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#define I2SIP_DMA_CTRL_RX_ENABLE_SHIFT (0)
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#define I2SIP_DMA_CTRL_RX_ENABLE_MASK ((0x1)<<I2SIP_DMA_CTRL_RX_ENABLE_SHIFT)
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#define I2SIP_DMA_CTRL_TX_ENABLE_SHIFT (1)
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#define I2SIP_DMA_CTRL_TX_ENABLE_MASK ((0x1)<<I2SIP_DMA_CTRL_TX_ENABLE_SHIFT)
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#else
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#define I2SIP_DMA_CTRL_REG_OFFSET 0x1c8
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#define I2SIP_DMA_CTRL_RX_ENABLE_SHIFT (0)
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#define I2SIP_DMA_CTRL_RX_ENABLE_MASK ((0x1)<<I2SIP_DMA_CTRL_RX_ENABLE_SHIFT)
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#define I2SIP_DMA_CTRL_TX_ENABLE_SHIFT (1)
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#define I2SIP_DMA_CTRL_TX_ENABLE_MASK ((0x1)<<I2SIP_DMA_CTRL_TX_ENABLE_SHIFT)
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#define I2SIP_DMA_CTRL_RX_1_CHAN_SHIFT (2)
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#define I2SIP_DMA_CTRL_RX_1_CHAN_MASK (1 << I2SIP_DMA_CTRL_RX_1_CHAN_SHIFT)
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#define I2SIP_DMA_CTRL_TX_1_CHAN_SHIFT (3)
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#define I2SIP_DMA_CTRL_TX_1_CHAN_MASK (1 << I2SIP_DMA_CTRL_TX_1_CHAN_SHIFT)
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#define I2SIP_DMA_CTRL_RX_CHAN_SEL_SHIFT (4)
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#define I2SIP_DMA_CTRL_RX_CHAN_SEL_MASK (3 << I2SIP_DMA_CTRL_RX_CHAN_SEL_SHIFT)
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#define I2SIP_DMA_CTRL_RX_CHAN_SEL(n) BITFIELD_VAL(I2SIP_DMA_CTRL_RX_CHAN_SEL, n)
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#define I2SIP_DMA_CTRL_TX_CHAN_SEL_SHIFT (6)
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#define I2SIP_DMA_CTRL_TX_CHAN_SEL_MASK (3 << I2SIP_DMA_CTRL_TX_CHAN_SEL_SHIFT)
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#define I2SIP_DMA_CTRL_TX_CHAN_SEL(n) BITFIELD_VAL(I2SIP_DMA_CTRL_TX_CHAN_SEL, n)
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#define I2SIP_DMA_CTRL_RX_DMA_BLK_SIZE_SHIFT (16)
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#define I2SIP_DMA_CTRL_RX_DMA_BLK_SIZE_MASK (0xF << I2SIP_DMA_CTRL_RX_DMA_BLK_SIZE_SHIFT)
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#define I2SIP_DMA_CTRL_RX_DMA_BLK_SIZE(n) BITFIELD_VAL(I2SIP_DMA_CTRL_RX_DMA_BLK_SIZE, n)
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#define I2SIP_DMA_CTRL_RX_FIFO_PUSH_REALIGN_SHIFT (20)
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#define I2SIP_DMA_CTRL_RX_FIFO_PUSH_REALIGN_MASK (1 << I2SIP_DMA_CTRL_RX_FIFO_PUSH_REALIGN_SHIFT)
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#define I2SIP_DMA_CTRL_RX_FIFO_POP_REALIGN_SHIFT (21)
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#define I2SIP_DMA_CTRL_RX_FIFO_POP_REALIGN_MASK (1 << I2SIP_DMA_CTRL_RX_FIFO_POP_REALIGN_SHIFT)
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#define I2SIP_DMA_CTRL_RX_DMA_BLK_EN_SHIFT (22)
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#define I2SIP_DMA_CTRL_RX_DMA_BLK_EN_MASK (1 << I2SIP_DMA_CTRL_RX_DMA_BLK_EN_SHIFT)
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#define I2SIP_DMA_CTRL_TX_DMA_BLK_SIZE_SHIFT (24)
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#define I2SIP_DMA_CTRL_TX_DMA_BLK_SIZE_MASK (0xF << I2SIP_DMA_CTRL_TX_DMA_BLK_SIZE_SHIFT)
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#define I2SIP_DMA_CTRL_TX_DMA_BLK_SIZE(n) BITFIELD_VAL(I2SIP_DMA_CTRL_TX_DMA_BLK_SIZE, n)
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#define I2SIP_DMA_CTRL_TX_FIFO_PUSH_REALIGN_SHIFT (28)
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#define I2SIP_DMA_CTRL_TX_FIFO_PUSH_REALIGN_MASK (1 << I2SIP_DMA_CTRL_TX_FIFO_PUSH_REALIGN_SHIFT)
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#define I2SIP_DMA_CTRL_TX_FIFO_POP_REALIGN_SHIFT (29)
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#define I2SIP_DMA_CTRL_TX_FIFO_POP_REALIGN_MASK (1 << I2SIP_DMA_CTRL_TX_FIFO_POP_REALIGN_SHIFT)
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#define I2SIP_DMA_CTRL_TX_DMA_BLK_EN_SHIFT (30)
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#define I2SIP_DMA_CTRL_TX_DMA_BLK_EN_MASK (1 << I2SIP_DMA_CTRL_TX_DMA_BLK_EN_SHIFT)
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#endif
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/* tdm ctrl register */
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#define I2SIP_TDM_CTRL_REG_OFFSET 0x1d0
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/* channel 0 end */
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/* i2s trigger register */
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#define I2SIP_EN_SEL_OFFSET 0x1d4
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#define I2SIP_TX_EN_SEL_SHIFT (0)
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#define I2SIP_TX_EN_SEL_MASK ((0x3)<<I2SIP_TX_EN_SEL_SHIFT)
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#define I2SIP_TX_EN_SEL(n) BITFIELD_VAL(I2SIP_TX_EN_SEL, n)
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#define I2SIP_RX_EN_SEL_SHIFT (2)
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#define I2SIP_RX_EN_SEL_MASK ((0x3)<<I2SIP_RX_EN_SEL_SHIFT)
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#define I2SIP_RX_EN_SEL(n) BITFIELD_VAL(I2SIP_RX_EN_SEL, n)
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#define I2SIP_CLK_EN_SEL_SHIFT (4)
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#define I2SIP_CLK_EN_SEL_MASK ((0x3)<<I2SIP_CLK_EN_SEL_SHIFT)
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#define I2SIP_CLK_EN_SEL(n) BITFIELD_VAL(I2SIP_CLK_EN_SEL, n)
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/* i2sip register end */
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#endif /* __REG_I2SIP_H_ */
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