294 lines
11 KiB
C
294 lines
11 KiB
C
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/***************************************************************************
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*
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* Copyright 2015-2019 BES.
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* All rights reserved. All unpublished rights reserved.
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*
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* No part of this work may be used or reproduced in any form or by any
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* means, or stored in a database or retrieval system, without prior written
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* permission of BES.
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*
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* Use of this work is governed by a license granted by BES.
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* This work contains confidential and proprietary information of
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* BES. which is protected by copyright, trade secret,
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* trademark and other intellectual property rights.
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*
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****************************************************************************/
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#ifndef __HAL_DMA_H__
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#define __HAL_DMA_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "stdint.h"
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#include "stdbool.h"
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#define HAL_DMA_CHAN_NONE 0xFF
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#define HAL_DMA_MAX_DESC_XFER_SIZE 0xFFF
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enum HAL_DMA_RET_T {
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HAL_DMA_OK,
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HAL_DMA_ERR,
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};
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enum HAL_DMA_GET_CHAN_T {
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HAL_DMA_HIGH_PRIO,
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HAL_DMA_LOW_PRIO,
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HAL_DMA_LOW_PRIO_ONLY
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};
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// DMA Type of DMA controller
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enum HAL_DMA_FLOW_CONTROL_T {
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HAL_DMA_FLOW_M2M_DMA = 0, /* Memory to memory - DMA control */
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HAL_DMA_FLOW_M2P_DMA = 1, /* Memory to peripheral - DMA control */
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HAL_DMA_FLOW_P2M_DMA = 2, /* Peripheral to memory - DMA control */
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HAL_DMA_FLOW_P2P_DMA = 3, /* Source peripheral to destination peripheral - DMA control */
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HAL_DMA_FLOW_P2P_DSTPERIPH = 4, /* Source peripheral to destination peripheral - destination peripheral control */
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HAL_DMA_FLOW_M2P_PERIPH = 5, /* Memory to peripheral - peripheral control */
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HAL_DMA_FLOW_P2M_PERIPH = 6, /* Peripheral to memory - peripheral control */
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HAL_DMA_FLOW_P2P_SRCPERIPH = 7, /* Source peripheral to destination peripheral - source peripheral control */
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HAL_DMA_FLOW_FLAG_SI = 0x40,
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HAL_DMA_FLOW_FLAG_DI = 0x80,
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HAL_DMA_FLOW_FLAG_MASK = (HAL_DMA_FLOW_FLAG_SI | HAL_DMA_FLOW_FLAG_DI),
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HAL_DMA_FLOW_M2P_DI_DMA = HAL_DMA_FLOW_M2P_DMA | HAL_DMA_FLOW_FLAG_DI,
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HAL_DMA_FLOW_P2M_SI_DMA = HAL_DMA_FLOW_P2M_DMA | HAL_DMA_FLOW_FLAG_SI,
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HAL_DMA_FLOW_P2P_DI_DMA = HAL_DMA_FLOW_P2P_DMA | HAL_DMA_FLOW_FLAG_DI,
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HAL_DMA_FLOW_P2P_SI_DMA = HAL_DMA_FLOW_P2P_DMA | HAL_DMA_FLOW_FLAG_SI,
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};
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// DMA Burst size in Source and Destination definitions
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enum HAL_DMA_BSIZE_T {
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HAL_DMA_BSIZE_1 = 0, /* Burst size = 1 */
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HAL_DMA_BSIZE_4 = 1, /* Burst size = 4 */
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HAL_DMA_BSIZE_8 = 2, /* Burst size = 8 */
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HAL_DMA_BSIZE_16 = 3, /* Burst size = 16 */
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HAL_DMA_BSIZE_32 = 4, /* Burst size = 32 */
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HAL_DMA_BSIZE_64 = 5, /* Burst size = 64 */
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HAL_DMA_BSIZE_128 = 6, /* Burst size = 128 */
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HAL_DMA_BSIZE_256 = 7, /* Burst size = 256 */
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};
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// Width in Source transfer width and Destination transfer width definitions
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enum HAL_DMA_WDITH_T {
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HAL_DMA_WIDTH_BYTE = 0, /* Width = 1 byte */
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HAL_DMA_WIDTH_HALFWORD = 1, /* Width = 2 bytes */
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HAL_DMA_WIDTH_WORD = 2, /* Width = 4 bytes */
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};
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enum HAL_DMA_PERIPH_T {
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HAL_DMA_PERIPH_NULL = 0,
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HAL_GPDMA_MEM = 1,
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HAL_AUDMA_MEM = 2,
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HAL_GPDMA_SDIO = 10,
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HAL_GPDMA_SDMMC = 11,
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HAL_GPDMA_I2C0_RX = 12,
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HAL_GPDMA_I2C0_TX = 13,
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HAL_GPDMA_SPI_RX = 14,
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HAL_GPDMA_SPI_TX = 15,
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HAL_GPDMA_SPILCD_RX = 16,
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HAL_GPDMA_SPILCD_TX = 17,
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HAL_GPDMA_UART0_RX = 18,
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HAL_GPDMA_UART0_TX = 19,
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HAL_GPDMA_UART1_RX = 20,
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HAL_GPDMA_UART1_TX = 21,
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HAL_GPDMA_ISPI_RX = 22,
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HAL_GPDMA_ISPI_TX = 23,
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HAL_GPDMA_UART2_RX = 24,
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HAL_GPDMA_UART2_TX = 25,
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HAL_GPDMA_FLASH_RX = 26,
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HAL_GPDMA_FLASH_TX = 27,
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HAL_GPDMA_I2C1_RX = 28,
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HAL_GPDMA_I2C1_TX = 29,
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HAL_GPDMA_I2C2_RX = 30,
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HAL_GPDMA_I2C2_TX = 31,
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HAL_GPDMA_I2C3_RX = 32,
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HAL_GPDMA_I2C3_TX = 33,
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HAL_AUDMA_CODEC_RX = 50,
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HAL_AUDMA_CODEC_TX = 51,
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HAL_AUDMA_BTPCM_RX = 52,
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HAL_AUDMA_BTPCM_TX = 53,
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HAL_AUDMA_I2S0_RX = 54,
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HAL_AUDMA_I2S0_TX = 55,
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HAL_AUDMA_DPD_RX = 56,
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HAL_AUDMA_DPD_TX = 57,
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HAL_AUDMA_SPDIF0_RX = 58,
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HAL_AUDMA_SPDIF0_TX = 59,
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HAL_AUDMA_SPDIF1_RX = 60,
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HAL_AUDMA_SPDIF1_TX = 61,
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HAL_AUDMA_DSD_RX = 62,
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HAL_AUDMA_DSD_TX = 63,
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HAL_AUDMA_MC_RX = 64,
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HAL_AUDMA_FFT_RX = 65,
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HAL_AUDMA_FFT_TX = 66,
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HAL_AUDMA_FIR_RX = 67,
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HAL_AUDMA_FIR_TX = 68,
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HAL_AUDMA_IIR_RX = 69,
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HAL_AUDMA_IIR_TX = 70,
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HAL_AUDMA_BTDUMP = 71,
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HAL_AUDMA_I2S1_RX = 72,
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HAL_AUDMA_I2S1_TX = 73,
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HAL_AUDMA_FM_RX = 74,
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HAL_AUDMA_FMDUMP0 = 75,
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HAL_AUDMA_FMDUMP1 = 76,
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HAL_AUDMA_CODEC_TX2 = 77,
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HAL_DMA_PERIPH_QTY,
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};
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struct HAL_DMA_DESC_T;
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typedef void (*HAL_DMA_IRQ_HANDLER_T)(uint8_t chan, uint32_t remain_tsize, uint32_t error, struct HAL_DMA_DESC_T *lli);
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typedef void (*HAL_DMA_START_CALLBACK_T)(uint8_t chan);
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typedef void (*HAL_DMA_DELAY_FUNC)(uint32_t ms);
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// DMA structure using for DMA configuration
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struct HAL_DMA_CH_CFG_T {
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uint8_t ch; /* DMA channel number */
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uint8_t try_burst;
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uint16_t src_tsize; /* Length/Size of transfer */
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enum HAL_DMA_WDITH_T src_width;
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enum HAL_DMA_WDITH_T dst_width;
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enum HAL_DMA_BSIZE_T src_bsize;
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enum HAL_DMA_BSIZE_T dst_bsize;
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enum HAL_DMA_FLOW_CONTROL_T type; /* Transfer Type */
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enum HAL_DMA_PERIPH_T src_periph;
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enum HAL_DMA_PERIPH_T dst_periph;
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uint32_t src; /* Physical Source Address */
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uint32_t dst; /* Physical Destination Address */
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HAL_DMA_IRQ_HANDLER_T handler;
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HAL_DMA_START_CALLBACK_T start_cb;
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};
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// Transfer Descriptor structure typedef
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struct HAL_DMA_DESC_T {
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uint32_t src; /* Source address */
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uint32_t dst; /* Destination address */
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uint32_t lli; /* Pointer to next descriptor structure */
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uint32_t ctrl; /* Control word that has transfer size, type etc. */
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};
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// DMA 2D configuration structure
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struct HAL_DMA_2D_CFG_T {
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int16_t xmodify;
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uint16_t xcount;
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int16_t ymodify;
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uint16_t ycount;
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};
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struct HAL_DMA_BURST_ADDR_INC_T {
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bool src_inc_en;
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bool dst_inc_en;
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int16_t src_inc_val;
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int16_t dst_inc_val;
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};
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//=============================================================
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void hal_dma_open(void);
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void hal_dma_close(void);
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void hal_dma_sleep(void);
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void hal_dma_wakeup(void);
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bool hal_dma_chan_busy(uint8_t ch);
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uint8_t hal_dma_get_chan(enum HAL_DMA_PERIPH_T periph, enum HAL_DMA_GET_CHAN_T policy);
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void hal_dma_free_chan(uint8_t ch);
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uint32_t hal_dma_cancel(uint8_t ch);
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uint32_t hal_dma_stop(uint8_t ch);
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enum HAL_DMA_RET_T hal_dma_init_desc(struct HAL_DMA_DESC_T *desc,
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const struct HAL_DMA_CH_CFG_T *cfg,
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const struct HAL_DMA_DESC_T *next,
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int tc_irq);
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enum HAL_DMA_RET_T hal_dma_sg_start(const struct HAL_DMA_DESC_T *desc,
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const struct HAL_DMA_CH_CFG_T *cfg);
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enum HAL_DMA_RET_T hal_dma_sg_2d_start(const struct HAL_DMA_DESC_T *desc,
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const struct HAL_DMA_CH_CFG_T *cfg,
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const struct HAL_DMA_2D_CFG_T *src_2d,
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const struct HAL_DMA_2D_CFG_T *dst_2d);
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enum HAL_DMA_RET_T hal_dma_start(const struct HAL_DMA_CH_CFG_T *cfg);
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uint32_t hal_dma_get_cur_src_addr(uint8_t ch);
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uint32_t hal_dma_get_cur_dst_addr(uint8_t ch);
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void hal_dma_get_cur_src_remain_and_addr(uint8_t ch, uint32_t *remain, uint32_t *src);
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uint32_t hal_dma_get_sg_remain_size(uint8_t ch);
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enum HAL_DMA_RET_T hal_dma_irq_run_chan(uint8_t ch);
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bool hal_dma_busy(void);
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HAL_DMA_DELAY_FUNC hal_dma_set_delay_func(HAL_DMA_DELAY_FUNC new_func);
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void hal_dma_remap_periph(enum HAL_DMA_PERIPH_T periph, int enable);
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void hal_dma_tc_irq_enable(uint8_t ch);
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void hal_dma_tc_irq_disable(uint8_t ch);
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void hal_dma_set_burst_addr_inc(uint8_t ch, const struct HAL_DMA_BURST_ADDR_INC_T *inc);
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void hal_dma_clear_burst_addr_inc(uint8_t ch);
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void hal_dma_set_desc_burst_addr_inc(struct HAL_DMA_DESC_T *desc, const struct HAL_DMA_BURST_ADDR_INC_T *inc);
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void hal_dma_clear_desc_burst_addr_inc(struct HAL_DMA_DESC_T *desc);
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//=============================================================
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#define hal_audma_open hal_dma_open
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#define hal_audma_close hal_dma_close
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#define hal_audma_chan_busy hal_dma_chan_busy
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#define hal_audma_get_chan hal_dma_get_chan
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#define hal_audma_free_chan hal_dma_free_chan
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#define hal_audma_cancel hal_dma_cancel
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#define hal_audma_stop hal_dma_stop
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#define hal_audma_init_desc hal_dma_init_desc
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#define hal_audma_sg_start hal_dma_sg_start
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#define hal_audma_start hal_dma_start
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#define hal_audma_get_cur_src_addr hal_dma_get_cur_src_addr
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#define hal_audma_get_cur_dst_addr hal_dma_get_cur_dst_addr
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#define hal_audma_get_sg_remain_size hal_dma_get_sg_remain_size
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#define hal_audma_irq_run_chan hal_dma_irq_run_chan
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#define hal_gpdma_open hal_dma_open
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#define hal_gpdma_close hal_dma_close
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#define hal_gpdma_chan_busy hal_dma_chan_busy
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#define hal_gpdma_get_chan hal_dma_get_chan
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#define hal_gpdma_free_chan hal_dma_free_chan
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#define hal_gpdma_cancel hal_dma_cancel
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#define hal_gpdma_stop hal_dma_stop
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#define hal_gpdma_init_desc hal_dma_init_desc
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#define hal_gpdma_sg_start hal_dma_sg_start
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#define hal_gpdma_start hal_dma_start
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#define hal_gpdma_get_cur_src_addr hal_dma_get_cur_src_addr
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#define hal_gpdma_get_cur_dst_addr hal_dma_get_cur_dst_addr
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#define hal_gpdma_get_sg_remain_size hal_dma_get_sg_remain_size
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#define hal_gpdma_irq_run_chan hal_dma_irq_run_chan
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//=============================================================
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#ifdef __cplusplus
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}
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#endif
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#endif
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