176 lines
6.9 KiB
C
176 lines
6.9 KiB
C
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/***************************************************************************
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*
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* Copyright 2015-2019 BES.
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* All rights reserved. All unpublished rights reserved.
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*
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* No part of this work may be used or reproduced in any form or by any
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* means, or stored in a database or retrieval system, without prior written
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* permission of BES.
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*
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* Use of this work is governed by a license granted by BES.
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* This work contains confidential and proprietary information of
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* BES. which is protected by copyright, trade secret,
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* trademark and other intellectual property rights.
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*
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****************************************************************************/
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#ifndef __PLAT_ADDR_MAP_BEST2300P_H__
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#define __PLAT_ADDR_MAP_BEST2300P_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define ROM_BASE 0x00000000
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#ifndef ROM_SIZE
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#define ROM_SIZE 0x0000C000
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#endif
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#define RAMRET_BASE 0x200D8000
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#define RAMXRET_BASE 0x002D8000
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#ifndef RAMRET_SIZE
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#define RAMRET_SIZE 0x00020000
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#endif
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#define RAM0_BASE 0x20000000
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#define RAMX0_BASE 0x00200000
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#define RAM1_BASE 0x20020000
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#define RAMX1_BASE 0x00220000
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#define RAM2_BASE 0x20040000
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#define RAMX2_BASE 0x00240000
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#define RAM3_BASE 0x20060000
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#define RAMX3_BASE 0x00260000
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#define RAM4_BASE 0x20080000
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#define RAMX4_BASE 0x00280000
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#define RAM5_BASE 0x200A0000
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#define RAMX5_BASE 0x002A0000
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#define RAM6_BASE 0x200C0000
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#define RAMX6_BASE 0x002C0000
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#define RAM_BASE RAM0_BASE
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#define RAMX_BASE RAMX0_BASE
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#ifdef CHIP_HAS_CP
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#define RAMCP_TOP (RAMRET_BASE + RAMRET_SIZE - 0x20)
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#ifndef RAMCP_SIZE
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#define RAMCP_SIZE (RAMRET_SIZE - 0x20)
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#endif
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#define RAMCP_BASE (RAMCP_TOP - RAMCP_SIZE)
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#ifndef RAMCPX_SIZE
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#define RAMCPX_SIZE (RAMXRET_BASE - RAMX6_BASE)
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#endif
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#ifndef RAMCPX_BASE
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#define RAMCPX_BASE (RAM_TO_RAMX(RAMCP_BASE) - RAMCPX_SIZE)
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#endif
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#endif
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#ifndef RAM_SIZE
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#ifdef CHIP_HAS_CP
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#define RAM_SIZE (RAMCPX_BASE - RAMX_BASE) // 0X000C0000
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#else
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#ifdef LARGE_RAM
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#define RAM_SIZE (RAMRET_BASE + RAMRET_SIZE - RAM_BASE) // 0x000F8000
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#else
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#define RAM_SIZE (RAMRET_BASE - RAM_BASE) // 0x000D8000
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#endif
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#endif /* !CHIP_HAS_CP */
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#endif /* !RAM_SIZE */
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#if defined(ROM_BUILD) && defined(CORE_SLEEP_POWER_DOWN)
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#undef RAM_BASE
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#undef RAMX_BASE
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#undef RAM_SIZE
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#define RAM_BASE RAMRET_BASE
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#define RAMX_BASE RAMXRET_BASE
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#define RAM_SIZE RAMRET_SIZE
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#endif
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#define FLASH_BASE 0x3C000000
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#define FLASH_NC_BASE 0x38000000
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#define FLASHX_BASE 0x0C000000
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#define FLASHX_NC_BASE 0x08000000
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#define ICACHE_CTRL_BASE 0x07FFE000
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#define ICACHECP_CTRL_BASE 0x07FFA000
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/* No data cache */
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#define CMU_BASE 0x40000000
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#define MCU_WDT_BASE 0x40001000
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#define MCU_TIMER0_BASE 0x40002000
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#define MCU_TIMER1_BASE 0x40003000
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#define MCU_TIMER2_BASE 0x40004000
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#define I2C0_BASE 0x40005000
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#define I2C1_BASE 0x40006000
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#define SPI_BASE 0x40007000
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#define SPILCD_BASE 0x40008000
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#define ISPI_BASE 0x40009000
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#define SPIPHY_BASE 0x4000A000
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#define UART0_BASE 0x4000B000
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#define UART1_BASE 0x4000C000
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#define UART2_BASE 0x4000D000
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#define BTPCM_BASE 0x4000E000
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#define I2S0_BASE 0x4000F000
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#define SPDIF0_BASE 0x40010000
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#define I2S1_BASE 0x40011000
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#define SEC_ENG_BASE 0x40020000
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#define AON_CMU_BASE 0x40080000
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#define AON_GPIO_BASE 0x40081000
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#define AON_WDT_BASE 0x40082000
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#define AON_PWM_BASE 0x40083000
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#define AON_TIMER_BASE 0x40084000
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#define AON_PSC_BASE 0x40085000
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#define AON_IOMUX_BASE 0x40086000
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#define SDMMC_BASE 0x40110000
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#define AUDMA_BASE 0x40120000
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#define GPDMA_BASE 0x40130000
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#define FLASH_CTRL_BASE 0x40140000
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#define BTDUMP_BASE 0x40150000
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#define I2C_SLAVE_BASE 0x40160000
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#define SENSOR_ENG_BASE 0x40170000
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#define USB_BASE 0x40180000
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#define SEDMA_BASE 0x401D0000
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#define CODEC_BASE 0x40300000
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#define BT_SUBSYS_BASE 0xA0000000
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#define BT_RAM_BASE 0xC0000000
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#define BT_RAM_SIZE 0x00008000
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#define BT_EXCH_MEM_BASE 0xD0210000
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#define BT_EXCH_MEM_SIZE 0x00008000
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#define BT_UART_BASE 0xD0300000
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#define BT_CMU_BASE 0xD0330000
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#define IOMUX_BASE AON_IOMUX_BASE
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#define GPIO_BASE AON_GPIO_BASE
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#define PWM_BASE AON_PWM_BASE
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#ifdef CORE_SLEEP_POWER_DOWN
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#define TIMER0_BASE AON_TIMER_BASE
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#else
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#define TIMER0_BASE MCU_TIMER0_BASE
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#endif
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#define TIMER1_BASE MCU_TIMER1_BASE
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#define WDT_BASE AON_WDT_BASE
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/* For linker scripts */
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#define VECTOR_SECTION_SIZE 320
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#define REBOOT_PARAM_SECTION_SIZE 64
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#define ROM_BUILD_INFO_SECTION_SIZE 40
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#define ROM_EXPORT_FN_SECTION_SIZE 128
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#define BT_INTESYS_MEM_OFFSET 0x00000000
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/* For boot struct version */
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#ifndef SECURE_BOOT_VER
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#define SECURE_BOOT_VER 2
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif
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