89 lines
3.1 KiB
C
89 lines
3.1 KiB
C
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/***************************************************************************
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*
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* Copyright 2015-2019 BES.
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* All rights reserved. All unpublished rights reserved.
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*
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* No part of this work may be used or reproduced in any form or by any
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* means, or stored in a database or retrieval system, without prior written
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* permission of BES.
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*
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* Use of this work is governed by a license granted by BES.
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* This work contains confidential and proprietary information of
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* BES. which is protected by copyright, trade secret,
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* trademark and other intellectual property rights.
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*
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****************************************************************************/
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#ifndef NORFLASH_GD25Q32C_H
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#define NORFLASH_GD25Q32C_H
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#include "plat_types.h"
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/* bytes */
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#define GD25Q32C_PAGE_SIZE (256)
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#define GD25Q32C_SECTOR_SIZE (4096)
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#define GD25Q32C_BLOCK_SIZE (32*1024)
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#define GD25Q32C_TOTAL_SIZE (4*1024*1024)
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#define P25Q32L_TOTAL_SIZE (4*1024*1024)
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#define P25Q64L_TOTAL_SIZE (8*1024*1024)
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#define P25Q128L_TOTAL_SIZE (16*1024*1024)
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#define XM25QH16C_TOTAL_SIZE (2*1024*1024)
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#define XM25QH80B_TOTAL_SIZE (1*1024*1024)
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/* device cmd */
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#define GD25Q32C_CMD_ID 0x9F
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#define GD25Q32C_CMD_WRITE_ENABLE 0x06
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#define GD25Q32C_CMD_PAGE_PROGRAM 0x02
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#define GD25Q32C_CMD_DUAL_PAGE_PROGRAM 0xA2
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#define GD25Q32C_CMD_QUAD_PAGE_PROGRAM 0x32
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#define GD25Q32C_CMD_BLOCK_ERASE_32K 0x52
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#define GD25Q32C_CMD_BLOCK_ERASE_64K 0xD8
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#define GD25Q32C_CMD_BLOCK_ERASE GD25Q32C_CMD_BLOCK_ERASE_32K
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#define GD25Q32C_CMD_SECTOR_ERASE 0x20
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#define GD25Q32C_CMD_CHIP_ERASE 0x60
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#define GD25Q32C_CMD_READ_STATUS_S0_S7 0x05
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#define GD25Q32C_CMD_READ_STATUS_S8_S15 0x35
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#define GD25Q32C_CMD_WRITE_STATUS_S0_S7 0x01
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#define GD25Q32C_CMD_WRITE_STATUS_S8_S15 0x31
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#define GD25Q32C_CMD_FAST_QUAD_IO_READ 0xEB
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#define GD25Q32C_CMD_FAST_QUAD_OUTPUT_READ 0x6B
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#define GD25Q32C_CMD_FAST_DUAL_IO_READ 0xBB
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#define GD25Q32C_CMD_FAST_DUAL_OUTPUT_READ 0x3B
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#define GD25Q32C_CMD_STANDARD_READ 0x03
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#define GD25Q32C_CMD_STANDARD_FAST_READ 0x0B
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#define GD25Q32C_CMD_DEEP_POWER_DOWN 0xB9
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#define GD25Q32C_CMD_RELEASE_FROM_DP 0xAB
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#define GD25Q32C_CMD_HIGH_PERFORMANCE 0xA3
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#define GD25Q32C_CMD_SET_BURST_WRAP 0x77
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#define GD25Q32C_CMD_UNIQUE_ID 0x4B
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#define GD25Q32C_CMD_ENABLE_RESET 0x66
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#define GD25Q32C_CMD_RESET 0x99
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#define GD25Q32C_CMD_PROGRAM_ERASE_SUSPEND 0x75
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#define GD25Q32C_CMD_PROGRAM_ERASE_RESUME 0x7A
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#define GD25Q32C_CMD_SECURITY_REGISTER_ERASE 0x44
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#define GD25Q32C_CMD_SECURITY_REGISTER_PROGRAM 0x42
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#define GD25Q32C_CMD_SECURITY_REGISTER_READ 0x48
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#define PUYA_FLASH_CMD_PAGE_ERASE 0x81
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/* status register _S0_S7*/
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#define GD25Q32C_WIP_BIT_SHIFT 0
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#define GD25Q32C_WIP_BIT_MASK ((0x1)<<GD25Q32C_WIP_BIT_SHIFT)
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#define GD25Q32C_WEL_BIT_SHIFT 1
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#define GD25Q32C_WEL_BIT_MASK ((0x1)<<GD25Q32C_WEL_BIT_SHIFT)
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#define GD25Q32C_BP0_4_BIT_SHIFT 2
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#define GD25Q32C_BP0_4_BIT_MASK ((0x1F)<<GD25Q32C_WEL_BIT_SHIFT)
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#define GD25Q32C_BP0_4_BIT(n) (((n) & 0x1F)<<GD25Q32C_WEL_BIT_SHIFT)
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/* status register _S8_S15*/
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#define GD25Q32C_QE_BIT_SHIFT 1
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#define GD25Q32C_QE_BIT_MASK ((0x1)<<GD25Q32C_QE_BIT_SHIFT)
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#define GD25Q32C_CMP_BIT_SHIFT 6
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#define GD25Q32C_CMP_BIT_MASK ((0x1)<<GD25Q32C_CMP_BIT_SHIFT)
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#endif /* NORFLASH_GD25Q32C_H */
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