104 lines
3.7 KiB
C
104 lines
3.7 KiB
C
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/**************************************************************************//**
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* @file mem_ARMCA7.h
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* @brief Memory base and size definitions (used in scatter file)
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* @version V1.1.0
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* @date 15. May 2019
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*
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* @note
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*
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******************************************************************************/
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/*
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* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef __MEM_ARMCA7_H
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#define __MEM_ARMCA7_H
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/*----------------------------------------------------------------------------
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User Stack & Heap size definition
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*----------------------------------------------------------------------------*/
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/*
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//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
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*/
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#if 0
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/*--------------------- ROM Configuration ------------------------------------
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//
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// <h> ROM Configuration
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// <i> For compatibility with MMU config the sections must be multiple of 1MB
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// <o0> ROM Base Address <0x0-0xFFFFFFFF:0x100000>
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// <o1> ROM Size (in Bytes) <0x0-0xFFFFFFFF:0x100000>
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// </h>
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*----------------------------------------------------------------------------*/
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#define __ROM_BASE 0x80000000
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#define __ROM_SIZE 0x00200000
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/*--------------------- RAM Configuration -----------------------------------
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// <h> RAM Configuration
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// <i> For compatibility with MMU config the sections must be multiple of 1MB
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// <o0> RAM Base Address <0x0-0xFFFFFFFF:0x100000>
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// <o1> RAM Total Size (in Bytes) <0x0-0xFFFFFFFF:0x100000>
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// <h> Data Sections
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// <o2> RW_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8>
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// <o3> ZI_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8>
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// </h>
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// <h> Stack / Heap Configuration
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// <o4> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
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// <o5> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
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// <h> Exceptional Modes
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// <o6> UND Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
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// <o7> ABT Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
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// <o8> SVC Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
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// <o9> IRQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
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// <o10> FIQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
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// </h>
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// </h>
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// </h>
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*----------------------------------------------------------------------------*/
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#define __RAM_BASE 0x80200000
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#define __RAM_SIZE 0x00200000
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#define __RW_DATA_SIZE 0x00100000
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#define __ZI_DATA_SIZE 0x000F0000
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#define __STACK_SIZE 0x00001000
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#define __HEAP_SIZE 0x00008000
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#define __UND_STACK_SIZE 0x00000100
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#define __ABT_STACK_SIZE 0x00000100
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#define __SVC_STACK_SIZE 0x00000100
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#define __IRQ_STACK_SIZE 0x00000100
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#define __FIQ_STACK_SIZE 0x00000100
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/*----------------------------------------------------------------------------*/
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/*--------------------- TTB Configuration ------------------------------------
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//
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// <h> TTB Configuration
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// <i> The TLB L1 contains 4096 32-bit entries and must be 16kB aligned
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// <i> The TLB L2 entries are placed after the L1 in the MMU config
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// <o0> TTB Base Address <0x0-0xFFFFFFFF:0x4000>
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// <o1> TTB Size (in Bytes) <0x0-0xFFFFFFFF:8>
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// </h>
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*----------------------------------------------------------------------------*/
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#define __TTB_BASE 0x80500000
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#define __TTB_SIZE 0x00005000
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#endif
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#endif /* __MEM_ARMCA7_H */
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