150 lines
8.0 KiB
C
150 lines
8.0 KiB
C
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/***************************************************************************
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*
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* Copyright 2015-2019 BES.
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* All rights reserved. All unpublished rights reserved.
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*
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* No part of this work may be used or reproduced in any form or by any
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* means, or stored in a database or retrieval system, without prior written
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* permission of BES.
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*
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* Use of this work is governed by a license granted by BES.
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* This work contains confidential and proprietary information of
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* BES. which is protected by copyright, trade secret,
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* trademark and other intellectual property rights.
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*
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****************************************************************************/
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#ifndef __REG_DMA_H__
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#define __REG_DMA_H__
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#include "plat_types.h"
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#include "stdint.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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// Number of channels on GPDMA and AUDMA
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#define DMA_NUMBER_CHANNELS 8
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// DMA Channel register block structure
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struct DMA_CH_T {
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__IO uint32_t SRCADDR; // 0x100+N*0x20 DMA Channel Source Address Register
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__IO uint32_t DSTADDR; // 0x104+N*0x20 DMA Channel Destination Address Register
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__IO uint32_t LLI; // 0x108+N*0x20 DMA Channel Linked List Item Register
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__IO uint32_t CONTROL; // 0x10C+N*0x20 DMA Channel Control Register
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__IO uint32_t CONFIG; // 0x110+N*0x20 DMA Channel Configuration Register
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uint32_t RESERVED1[3]; // 0x114+N*0x20
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};
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struct DMA_2D_CFG_T {
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__IO uint32_t SRCX; // 0x200+N*0x20 DMA 2D Source X Axis Register
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__IO uint32_t SRCY; // 0x204+N*0x20 DMA 2D Source Y Axis Register
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__IO uint32_t DSTX; // 0x208+N*0x20 DMA 2D Destination X Axis Register
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__IO uint32_t DSTY; // 0x20C+N*0x20 DMA 2D Destination Y Axis Register
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__IO uint32_t CTRL; // 0x210+N*0x20 DMA 2D Control Register
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__IO uint32_t SRC_INC; // 0x214+N*0x20 DMA source address increment (signed value) in burst mode
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__IO uint32_t DST_INC; // 0x218+N*0x20 DMA destination address increment (signed value) in burst mode
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uint32_t RESERVED2; // 0x21C+N*0x20
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};
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// DMA register block
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struct DMA_T {
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__I uint32_t INTSTAT; // 0x000 DMA Interrupt Status Register
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__I uint32_t INTTCSTAT; // 0x004 DMA Interrupt Terminal Count Request Status Register
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__O uint32_t INTTCCLR; // 0x008 DMA Interrupt Terminal Count Request Clear Register
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__I uint32_t INTERRSTAT; // 0x00C DMA Interrupt Error Status Register
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__O uint32_t INTERRCLR; // 0x010 DMA Interrupt Error Clear Register
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__I uint32_t RAWINTTCSTAT; // 0x014 DMA Raw Interrupt Terminal Count Status Register
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__I uint32_t RAWINTERRSTAT; // 0x018 DMA Raw Error Interrupt Status Register
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__I uint32_t ENBLDCHNS; // 0x01C DMA Enabled Channel Register
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__IO uint32_t SOFTBREQ; // 0x020 DMA Software Burst Request Register
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__IO uint32_t SOFTSREQ; // 0x024 DMA Software Single Request Register
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__IO uint32_t SOFTLBREQ; // 0x028 DMA Software Last Burst Request Register
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__IO uint32_t SOFTLSREQ; // 0x02C DMA Software Last Single Request Register
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__IO uint32_t DMACONFIG; // 0x030 DMA Configuration Register
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__IO uint32_t SYNC; // 0x034 DMA Synchronization Register
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uint32_t RESERVED0[50]; // 0x038
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struct DMA_CH_T CH[DMA_NUMBER_CHANNELS]; // 0x100
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struct DMA_2D_CFG_T _2D[DMA_NUMBER_CHANNELS]; // 0x200
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};
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// Macro defines for DMA channel control registers
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#define DMA_CONTROL_TRANSFERSIZE(n) ((((n) & 0xFFF) << 0)) // Transfer size
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#define DMA_CONTROL_TRANSFERSIZE_MASK (0xFFF << 0)
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#define DMA_CONTROL_TRANSFERSIZE_SHIFT (0)
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#define DMA_CONTROL_SBSIZE(n) ((((n) & 0x07) << 12)) // Source burst size
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#define DMA_CONTROL_DBSIZE(n) ((((n) & 0x07) << 15)) // Destination burst size
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#define DMA_CONTROL_SWIDTH(n) ((((n) & 0x07) << 18)) // Source transfer width
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#define DMA_CONTROL_SWIDTH_MASK (0x07 << 18)
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#define DMA_CONTROL_SWIDTH_SHIFT (18)
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#define DMA_CONTROL_DWIDTH(n) ((((n) & 0x07) << 21)) // Destination transfer width
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#define DMA_CONTROL_BURST_SI ((1UL << 24)) // Source increment in burst mode
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#define DMA_CONTROL_BURST_DI ((1UL << 25)) // Destination increment in burst mode
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#define DMA_CONTROL_SI ((1UL << 26)) // Source increment
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#define DMA_CONTROL_DI ((1UL << 27)) // Destination increment
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#define DMA_CONTROL_SRCAHB1 0
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#define DMA_CONTROL_DSTAHB1 0
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#define DMA_CONTROL_PROT1 ((1UL << 28)) // Indicates that the access is in user mode or privileged mode
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#define DMA_CONTROL_PROT2 ((1UL << 29)) // Indicates that the access is bufferable or not bufferable
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#define DMA_CONTROL_PROT3 ((1UL << 30)) // Indicates that the access is cacheable or not cacheable
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#define DMA_CONTROL_TC_IRQ ((1UL << 31)) // Terminal count interrupt enable bit
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// Macro defines for DMA Channel Configuration registers
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#define DMA_CONFIG_EN ((1UL << 0)) // DMA control enable
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#define DMA_CONFIG_SRCPERIPH(n) ((((n) & 0x1F) << 1)) // Source peripheral
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#define DMA_CONFIG_DSTPERIPH(n) ((((n) & 0x1F) << 6)) // Destination peripheral
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#define DMA_CONFIG_TRANSFERTYPE(n) ((((n) & 0x7) << 11)) // This value indicates the type of transfer
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#define DMA_CONFIG_ERR_IRQMASK ((1UL << 14)) // Interrupt error mask
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#define DMA_CONFIG_TC_IRQMASK ((1UL << 15)) // Terminal count interrupt mask
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#define DMA_CONFIG_LOCK ((1UL << 16)) // Lock
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#define DMA_CONFIG_ACTIVE ((1UL << 17)) // Active
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#define DMA_CONFIG_HALT ((1UL << 18)) // Halt
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#define DMA_CONFIG_TRY_BURST ((1UL << 19)) // Try burst
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#define DMA_STAT_CHAN(n) ((1 << (n)) & 0xFF)
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#define DMA_STAT_CHAN_ALL (0xFF)
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// Macro defines for DMA Configuration register
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#define DMA_DMACONFIG_EN (1 << 0) // DMA Controller enable
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#define DMA_DMACONFIG_AHB1_BIGENDIAN (1 << 1) // AHB Master endianness configuration
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#define DMA_DMACONFIG_AHB2_BIGENDIAN (1 << 2) // AHB Master endianness configuration
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#define DMA_DMACONFIG_TC_IRQ_EN(n) (((n) & 0xFF) << 4)
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#define DMA_DMACONFIG_TC_IRQ_EN_MASK (0xFF << 4)
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#define DMA_DMACONFIG_TC_IRQ_EN_SHIFT (4)
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#define DMA_DMACONFIG_CLK_EN_SHIFT 12
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#define DMA_DMACONFIG_CLK_EN_MASK (0xFF << DMA_DMACONFIG_CLK_EN_SHIFT)
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#define DMA_DMACONFIG_CLK_EN(n) BITFIELD_VAL(DMA_DMACONFIG_CLK_EN, n)
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// Macro defines for DMA 2D Configuration registers
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#define DMA_2D_MODIFY_SHIFT 11
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#define DMA_2D_MODIFY_MASK (0x1FFFFF << DMA_2D_MODIFY_SHIFT)
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#define DMA_2D_MODIFY(n) BITFIELD_VAL(DMA_2D_MODIFY, n)
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#define DMA_2D_COUNT_SHIFT 0
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#define DMA_2D_COUNT_MASK (0x7FF << DMA_2D_COUNT_SHIFT)
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#define DMA_2D_COUNT(n) BITFIELD_VAL(DMA_2D_COUNT, n)
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#define DMA_2D_CTRL_DST_EN (1 << 1)
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#define DMA_2D_CTRL_SRC_EN (1 << 0)
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// Macro defines for DMA Burst Address Inc registers
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#define DMA_BURST_SRC_INC_VAL_SHIFT 0
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#define DMA_BURST_SRC_INC_VAL_MASK (0xFFFF << DMA_BURST_SRC_INC_VAL_SHIFT)
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#define DMA_BURST_SRC_INC_VAL(n) BITFIELD_VAL(DMA_BURST_SRC_INC_VAL, n)
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#define DMA_BURST_DST_INC_VAL_SHIFT 0
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#define DMA_BURST_DST_INC_VAL_MASK (0xFFFF << DMA_BURST_DST_INC_VAL_SHIFT)
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#define DMA_BURST_DST_INC_VAL(n) BITFIELD_VAL(DMA_BURST_DST_INC_VAL, n)
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#ifdef __cplusplus
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}
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#endif
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#endif
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